Disclaimer: This information is provided as is. There may be errors in this information. You may use this information only if you agree that Minimalist / Coinop.org, its employees, and noted authors will never be held responsible for any damage, injury, death, mayhem, etc. caused by errors in the information. When working with high voltage, never work alone and always follow safety precautions.

Document Title: [LIST-IClist.html (html file)]

IC List

Timing information for ICs is not yet available, and only TTL, 4000-series
CMOS and some microprocessor (support) chips are included.  For now, it is
not clear how the format used can be extended to include linear ICs, as these
usually require much more additional information such as a block diagram.

The current file uses the PC8 character set (a.k.a. codepage 437), but can
be converted to 7-bit ASCII without too much trouble (losing some niceties).
As it is, it is small and simple enough to keep it in your notebook PC for
when you are out in the field, it even fits in a HP100LX palmtop PC.
It might be possible to create a mail-server so that it may be accessed by
novice users of sci.electronics.  For now, I am unable to run a mail-server
on my login account, but perhaps someone will volunteer.

To minimize the amount of information needed per IC, a structured format
is used in the descriptions, and only features that differ from the
assumptions below are indicated.  Truth tables are not yet available for
all ICs, simply because creating them takes a long time.
The layout of the file is dictated by the fortune-cookie program I use to
sort this file (alphabetically -- not by number).

Anyone wanting to add this information should feel free to do so, but
please to not post changed versions.  Instead, mail additions to
falstaff@xs4all.nl.

Frank



PIN IDENTIFICATION
==================

General:
 * Missing pins have no pin number.
 * Unconnected pins and test pins that should be left floating have no
   identification.
 * Clock signals are identified by CLK for positive-edge triggering or /CLK
   for negative-edge triggering.
 * Reset (clear) inputs are identified by RST.
 * Set inputs are identified by SET.
 * For 3-state devices, output enables are indicated by OE.
 * When a pin has two modes, or selects between two operations, then the
   two may be separated by a slash.  An inversion slash may still be present
   as in SH//LD for shift or load select.
 * Pins that have more than one function (selected by programming or the state
   of another pin) are indicated by both functions separated by a space.

Power supply:
 * The main power supply is indicated by VCC.
 * System ground is indicated by GND.
 * A secondary positive power supply may be indicated by VDD.
 * A negative power supply is indicated by VEE.
 * Programming power supply (usually higher than VCC) is indicated by VPP.

Gates, line drivers etc.:
 * Inputs are identified by letters starting from A.
 * Outputs are indicated by Y.

Flip-flops:
 * Inputs are identified by J and K, or D.
 * Outputs are indicated by Q.

Counters:
 * Load inputs are indicated by P followed by the counter stage number.
 * Outputs are indicated by Q followed by the counter stage number.
   Thus (assuming a binary counter) Q0 is the /2 output, Q1 the /4 output.

Shift registers:
 * Parallel inputs or bidirectional parallel I/O pins are identified by P
   followed by the shifter stage number. The rightmost stage in a shift
   register is number 0.
 * Serial inputs are identified by letters starting from D (for right shift)
   or from L (for left shift).  If more than one of either is available,
   the letter is followed by the shifter stage number it feeds.
 * Serial outputs are identified by Q, which may be followed by the shifter
   stage number if more than one serial output exists.
 * Parallel outputs are identified by Q (only if no serial outputs exist),
   Y (3-state outputs or output latch) or R (otherwise) followed by the
   shifter stage number.
 * Unidirectional shift registers shift to the right (towards stage 0).

Multiplexers:
 * Inputs are identified by A followed by a number.
 * Outputs are indicated by Y.
 * Select inputs are identified by S followed by a number starting at 0,
   unless there is only one select input in which case only S is specified.
   When the S inputs are taken as a binary number, the value indicates
   which input is selected.

Demultiplexers:
 * Inputs are indicated by A, preceded by a section number if more than one.
 * Outputs are identified by Y followed by a number.  When there is more than
   one multiplexer section, inputs are prefixed by a number indicating to
   which section they belong.
 * Select inputs are identified by S followed by a number starting at 0,
   unless there is only one select input in which only S is specified.
   When the S inputs are taken as a binary number, the value indicates
   which output is selected.  For noninverting demultiplexers unselected
   outputs are 0, for inverting demultiplexers they are 1.

Analog multiplexers/demultiplexers:
 * Analog switches generally are bidirectional, and inputs and outputs can
   therefore be reversed.
   One side of the switch is indicated by X (optionally followed by a number),
   the other side is indicated by Y.
 * Select inputs are identified by S followed by a number starting at 0,
   unless there is only one select input in which only S is specified.
   When the S inputs are taken as a binary number, the value indicates
   which switch is selected.

Memories:
 * Address inputs are indicated by A followed by the bit number, starting
   from 0.  Multiport memories use RA or WA for separate read and write
   addresses, or A prefixed by the port number followed by the bit number.
 * Data inputs or data I/O are indicated by D followed by a number starting
   from 0.
 * Data outputs are indicated by Q followed by a number.

Oscillators:
 * One-inverter oscillators are indicated by X0 and X1 pins, where X0 is
   the inverters' output and X1 is the input.  If I happen not to know which
   is which, the pins are indicated by X1 and X2.  A crystal oscillator
   usually requires a crystal parallel to a 10M resistor, with two small
   capacitors to ground; but sometimes only a crystal is needed -- most
   often when a 32kHz watch crystal can be used.
 * Two-inverter oscillators are indicated by X1 (input), X0 (middle node)
   and X2 (output).  A crystal oscillator can then be made using X0 and X1.

Sections:
 * When a device has several (largely) independent sections, I/O pins
   are prefixed by the section number, starting from 1, as in 1J or /1Q.
 * Multi-bit functions, such as counters or 3-state buffers have I/O pins
   suffixed by the bit number, usually starting from 0 (except sometimes
   for counters which may have some outputs missing).
 * The section/bit numbering is used in a different way for (de)multiplexers.



TRUTH TABLES
============

For inputs, the following notations are used:
   0  : logic low level
   1  : logic high level
   X  : don't care, either 0 or 1
   /  : rising or positive-edge clock input
   \  : falling or negative-edge clock input
   !/ : not a rising edge, either 0, 1 or \
   !\ : not a falling edge, either 0, 1 or /
   .  : 'continued', used in compressing the table

For outputs, the following notations are used:
   0 : logic low level
   1 : logic high level
   Z : high impedance, either 3-state or open-collector not driving output
   - : no change (latched in closed state, or register value not changed)
   ? : undefined (although some manufacturers may define a behaviour)
   . : 'continued', used in compressing the table



ASSUMPTIONS FOR TTL DEVICES
===========================

Single/Dual Flip-flops:
 * The clock is positive-edge triggered.
 * Complementary outputs are available.

Multiple flip-flops:
 * Only inverting or noninverting outputs are available.

Synchronous counters:
 * The clock is positive-edge triggered.
 * LOAD,SET and RESET are synchronous.

Asynchronous counters:
 * The clock is negative-edge triggered.
 * LOAD,SET and RESET are asynchronous.

Shift registers:
 * The clock is positive-edge triggered.
 * LOAD and RESET (if available) are synchronous.


------------------------------------------------------------------------------
#
1458
Dual 741-type operational amplifiers.

     ����������Ŀ
1OUT �1  ����  8� VCC
-1In �2        7� 2OUT
+1In �3  1458  6� -2In
 VEE �4        5� +2In
     ������������
#
1488, 75188
TTL to RS232 level shifter.
The outputs are at RS-232 levels, and sometimes are connected to ground
through a small capacitor (up to 470 pF) to reduce slew-rate.
Note that 1B is missing (and can be taken to be 1 at all times).
Usually VDD=+12 and VEE=-12.

    ����������Ŀ          �������������Ŀ
VEE �1  ���� 14� VDD      � A � B �  Y  �
 1A �2       13� 4A       �������������͵
 1Y �3       12� 4B       � 0 � 0 � VDD �
 2A �4  1488 11� 4Y       � 0 � 1 � VDD �
 2B �5       10� 3A       � 1 � 0 � VDD �
 2Y �6        9� 3B       � 1 � 1 � VEE �
GND �7        8� 3Y       ���������������
    ������������
#
1489, 75189
RS232 to TTL level shifter.
A inputs are RS232-level inputs, C inputs are response control, a TTL
signal which could be used to adjust threshhold and hysteresis but is
generally unnecessary and unused. It is often tied through a 300 - 470 pF
capacitor to ground.

    ����������Ŀ
 1A �1  ���� 14� VCC
 1C �2       13� 4A
 1Y �3       12� 4C
 2A �4  1489 11� 4Y
 2C �5       10� 3A
 2Y �6        9� 3C
GND �7        8� 3Y
    ������������
#
16550
Asynchronous serial interface controller with DMA support and 16-byte FIFOs.

        ��������������Ŀ
     D0 �1    ����   40� VCC
     D1 �2           39� /RI
     D2 �3           38� /DCD
     D3 �4           37� /DSR
     D4 �5           36� /CTS
     D5 �6           35� MR
     D6 �7           34� /OUT1
     D7 �8           33� /DTR
   RCLK �9           32� /RTS
    SIN �10  16550   31� /OUT2
   SOUT �11          30� INTR
    CS0 �12          29� /RXRDY
    CS1 �13          28� A0
   /CS2 �14          27� A1
/CLKOUT �15          26� A2
     X1 �16          25� /ADS
     X0 �17          24� /TXRDY
    /WR �18          23� DDIS
     WR �19          22� RD
    GND �20          21� /RD
        ����������������
#
2401
I�C 128x8 EEPROM with write protect.
Address is 1010xxx where x can be specified by the A0-2 inputs.

    ����������Ŀ
 A0 �1  ����  8� VCC
 A1 �2        7� WP
 A2 �3  2401  6� SCL
GND �4        5� SDA
    ������������
#
2402
I�C 256x8 EEPROM with write protect.
Address is 1010xxx where x can be specified by the A0-2 inputs.

    ����������Ŀ
 A0 �1  ����  8� VCC
 A1 �2        7� WP
 A2 �3  2402  6� SCL
GND �4        5� SDA
    ������������
#
2404
I�C 2x256x8 EEPROM with write protect.
Address is 1010xxy where x can be specified by the A1-2 inputs,
and y selects the 256-byte bank to use.
A0 has no function, but must be connected to GND or VCC.

    ����������Ŀ
 A0 �1  ����  8� VCC
 A1 �2        7� WP
 A2 �3  2404  6� SCL
GND �4        5� SDA
    ������������
#
2408
I�C 4x256x8 EEPROM with write protect.
Address is 1010xyy where x can be specified by the A2 input,
and yy selects the 256-byte bank to use.
A0-1 have no function, but must be connected to GND or VCC.

    ����������Ŀ
 A0 �1  ����  8� VCC
 A1 �2        7� WP
 A2 �3  2408  6� SCL
GND �4        5� SDA
    ������������
#
2416
I�C 8x256x8 EEPROM with write protect.
Address is 1010yyy where yyy selects the 256-byte bank to use.
A0-2 have no function, but must be connected to GND or VCC.

    ����������Ŀ
 A0 �1  ����  8� VCC
 A1 �2        7� WP
 A2 �3  2416  6� SCL
GND �4        5� SDA
    ������������
#
2465
I�C 8kx8 EEPROM with programmable block write protect.
Address is 1010xxx where x can be specified by the A0-2 inputs.

    ����������Ŀ
 A0 �1  ����  8� VCC
 A1 �2        7� GND
 A2 �3  2465  6� SCL
GND �4        5� SDA
    ������������
#
271001
128kx8 EPROM.

    ��������������Ŀ
VPP �1    ����   32� VCC
A16 �2           31� /PGM
A15 �3           30�
A12 �4           29� A14
 A7 �5           28� A13
 A6 �6           27� A8
 A5 �7           26� A9
 A4 �8   271001  25� A11
 A3 �9           24� /OE
 A2 �10          23� A10
 A1 �11          22� /CE
 A0 �12          21� D7
 D0 �13          20� D6
 D1 �14          19� D5
 D2 �15          18� D4
GND �16          17� D3
    ����������������
#
271024
64kx16 EPROM.

    ��������������Ŀ
VPP �1    ����   40� VCC
/CE �2           39� /PGM
D15 �3           38�
D14 �4           37� A15
D13 �5           36� A14
D12 �6           35� A13
D11 �7           34� A12
D10 �8           33� A11
 D9 �9           32� A10
 D8 �10  271024  31� A9
GND �11          30� GND
 D7 �12          29� A8
 D6 �13          28� A7
 D5 �14          27� A6
 D4 �15          26� A5
 D3 �16          25� A4
 D2 �17          24� A3
 D1 �18          23� A2
 D0 �19          22� A1
/OE �20          21� A0
    ����������������
#
27128
16kx8 EPROM.
Available in 300 and 600 mil packages.

    ��������������Ŀ
VPP �1    ����   28� VCC
A12 �2           27� /PGM
 A7 �3           26� A13
 A6 �4           25� A8
 A5 �5           24� A9
 A4 �6           23� A11
 A3 �7   27128   22� /OE
 A2 �8           21� A10
 A1 �9           20� /CE
 A0 �10          19� D7
 D0 �11          18� D6
 D1 �12          17� D5
 D2 �13          16� D4
GND �14          15� D3
    ����������������
#
272001
256kx8 EPROM.

    ��������������Ŀ
VPP �1    ����   32� VCC
A16 �2           31� /PGM
A15 �3           30� A17
A12 �4           29� A14
 A7 �5           28� A13
 A6 �6           27� A8
 A5 �7           26� A9
 A4 �8   272001  25� A11
 A3 �9           24� /OE
 A2 �10          23� A10
 A1 �11          22� /CE
 A0 �12          21� D7
 D0 �13          20� D6
 D1 �14          19� D5
 D2 �15          18� D4
GND �16          17� D3
    ����������������
#
27256
32kx8 EPROM.
Available in 300 and 600 mil packages.

    ��������������Ŀ
VPP �1    ����   28� VCC
A12 �2           27� A14
 A7 �3           26� A13
 A6 �4           25� A8
 A5 �5           24� A9
 A4 �6           23� A11
 A3 �7   27256   22� /OE
 A2 �8           21� A10
 A1 �9           20� /CE
 A0 �10          19� D7
 D0 �11          18� D6
 D1 �12          17� D5
 D2 �13          16� D4
GND �14          15� D3
    ����������������
#
2732
4kx8 EPROM.

    ��������������Ŀ
 A7 �1    ����   24� VCC
 A6 �2           23� A8
 A5 �3           22� A9
 A4 �4           21� A11
 A3 �5           20� /OE VPP
 A2 �6    2732   19� A10
 A1 �7           18� /CE
 A0 �8           17� D7
 D0 �9           16� D6
 D1 �10          15� D5
 D2 �11          14� D4
GND �12          13� D3
    ����������������
#
274001
512kx8 EPROM.

    ��������������Ŀ
VPP �1    ����   32� VCC
A16 �2           31� A18
A15 �3           30� A17
A12 �4           29� A14
 A7 �5           28� A13
 A6 �6           27� A8
 A5 �7           26� A9
 A4 �8   274001  25� A11
 A3 �9           24� /OE
 A2 �10          23� A10
 A1 �11          22� /CE
 A0 �12          21� D7
 D0 �13          20� D6
 D1 �14          19� D5
 D2 �15          18� D4
GND �16          17� D3
    ����������������
#
27512
64kx8 EPROM.
Available in 300 and 600 mil packages.

    ��������������Ŀ
A15 �1    ����   28� VCC
A12 �2           27� A14
 A7 �3           26� A13
 A6 �4           25� A8
 A5 �5           24� A9
 A4 �6           23� A11
 A3 �7   27512   22� /OE VPP
 A2 �8           21� A10
 A1 �9           20� /CE
 A0 �10          19� D7
 D0 �11          18� D6
 D1 �12          17� D5
 D2 �13          16� D4
GND �14          15� D3
    ����������������
#
2764
8kx8 EPROM.
Available in 300 and 600 mil packages.

    ��������������Ŀ
VPP �1    ����   28� VCC
A12 �2           27� /PGM
 A7 �3           26�
 A6 �4           25� A8
 A5 �5           24� A9
 A4 �6           23� A11
 A3 �7    2764   22� /OE
 A2 �8           21� A10
 A1 �9           20� /CE
 A0 �10          19� D7
 D0 �11          18� D6
 D1 �12          17� D5
 D2 �13          16� D4
GND �14          15� D3
    ����������������
#
2864
8kx8 EEPROM.

    ��������������Ŀ
    �1    ����   28� VCC
A12 �2           27� /WE
 A7 �3           26�
 A6 �4           25� A8
 A5 �5           24� A9
 A4 �6           23� A11
 A3 �7    2864   22� /OE
 A2 �8           21� A10
 A1 �9           20� /CE
 A0 �10          19� D7
 D0 �11          18� D6
 D1 �12          17� D5
 D2 �13          16� D4
GND �14          15� D3
    ����������������
#
4000
Dual 3-input NOR gates and inverter.

    ����������Ŀ                ________
    �1  ���� 14� VCC        /1Y=1A+1B+1C
    �2       13� 3C
 1A �3       12� 3B             __
 1B �4  4000 11� 3A         /2Y=2A
 1C �5       10� /3Y
/1Y �6        9� /2Y            ________
GND �7        8� 2A         /3Y=3A+3B+3C
    ������������
#
4001
Quad 2-input NOR gates.

    ����������Ŀ             �����������Ŀ           ___
 1A �1  ���� 14� VCC         � A � B �/Y �      /Y = A+B
 1B �2       13� 4B          �����������͵
/1Y �3       12� 4A          � 0 � 0 � 1 �
/2Y �4  4001 11� /4Y         � 0 � 1 � 0 �
 2A �5       10� /3Y         � 1 � 0 � 0 �
 2B �6        9� 3B          � 1 � 1 � 0 �
GND �7        8� 3A          �������������
    ������������
#
4002, 744002
Dual 4-input NOR gates.

    ����������Ŀ             �������������������Ŀ       _________
/1Y �1  ���� 14� VCC         � A � B � C � D �/Y �  /Y = (A+B+C+D)
 1A �2       13� /2Y         �������������������͵
 1B �3       12� 2D          � 0 � 0 � 0 � 0 � 1 �
 1C �4  4002 11� 2C          � 0 � 0 � 0 � 1 � 0 �
 1D �5       10� 2B          � 0 � 0 � 1 � X � 0 �
    �6        9� 2A          � 0 � 1 � X � X � 0 �
GND �7        8�             � 1 � X � X � X � 0 �
    ������������             ���������������������
#
4006
Dual 4-bit and dual 5-bit serial-in serial-out shift registers.

     ����������Ŀ
 1D5 �1  ���� 14� VCC
/1Q4 �2       13� 1Q1
 CLK �3       12� 2Q0
 2D4 �4  4006 11� 2Q0
 3D4 �5       10� 3Q0
 4D5 �6        9� 4Q0
 GND �7        8� 4Q1
     ������������
#
4007
Dual complementary CMOS pair and unbuffered inverter.
For use as simple inverters, connect 1pS=3pS=VCC, 1nS=3nS=GND, 1pD=1nD=/1Y
and 2pD=2nD=/2Y.

     ����������Ŀ
 1pD �1  ���� 14� VCC
 1pS �2       13� 2pD
  1G �3       12� /3Y
 1nS �4  4007 11� 3pS
 1nD �5       10� 3G
  2G �6        9� 3nS
 GND �7        8� 2nD
     ������������
#
4008
4-bit binary full adder with fast carry.

    ����������Ŀ
 A3 �1  ���� 16� VCC         �=A+B+CIN
 B2 �2       15� B3
 A2 �3       14� CO
 B1 �4       13� �3
 A1 �5  4008 12� �2
 B0 �6       11� �1
 A0 �7       10� �0
GND �8        9� CI
    ������������
#
4009
Hex inverters with level shifted outputs.
VDD may not be lower than VCC.

    ����������Ŀ             �������Ŀ               _
VCC �1  ���� 16� VDD         � A �/Y �          /Y = A
/Y1 �2       15� /Y6         �������͵
 A1 �3       14� A6          � 0 � 1 �
/Y2 �4       13�             � 1 � 0 �
 A2 �5  4009 12� /Y5         ���������
/Y3 �6       11� A5
 A3 �7       10� /Y4
GND �8        9� A4
    ������������
#
4010
Hex buffers with level shifted outputs.
VDD may not be lower than VCC.

    ����������Ŀ             �������Ŀ
VCC �1  ���� 16� VDD         � A � Y �           Y = A
 Y1 �2       15� Y6          �������͵
 A1 �3       14� A6          � 0 � 0 �
 Y2 �4       13�             � 1 � 1 �
 A2 �5  4010 12� Y5          ���������
 Y3 �6       11� A5
 A3 �7       10� Y4
GND �8        9� A4
    ������������
#
40100
32-bit 3-state bidirectional serial-in serial-out shift register with separate
shift left and shift right serial in/outputs and both active high and active
low clocks.

      ����������Ŀ
      �1  ���� 16� VCC
/CLK2 �2       15�
 CLK1 �3       14�
  Q31 �4       13� L//R
      �5 40100 12� Q0
    L �6       11� D
      �7       10�
  GND �8        9� /LOOP
      ������������
#
40101
9-bit odd/even parity generator/checker.

    ����������Ŀ
 A0 �1  ���� 14� VCC
 A1 �2       13� A8
 A2 �3       12� A7
 A3 �4 40101 11� A6
 A4 �5       10� A5
ODD �6        9� EVEN
GND �7        8� /EN
    ������������
#
40102, 7440102
8-bit (2-digit) synchronous decade down counter with synchronous and
asynchronous load and reset.  Counter outputs only internally connected but
ripple carry and zero detect outputs available.

       ����������Ŀ
   CLK �1  ���� 16� VCC
  /RST �2       15� /SLD
/CLKEN �3       14� /RCO
    P0 �4       13� P7
    P1 �5 40102 12� P6
    P2 �6       11� P5
    P3 �7       10� P4
   GND �8        9� /ALD
       ������������
#
40103, 7440103
8-bit synchronous binary down counter with synchronous and asynchronous load
and reset.  Counter outputs only internally connected but ripple carry and
zero detect outputs available.

       ����������Ŀ
   CLK �1  ���� 16� VCC
  /RST �2       15� /SLD
/CLKEN �3       14� /RCO
    P0 �4       13� P7
    P1 �5 40103 12� P6
    P2 �6       11� P5
    P3 �7       10� P4
   GND �8        9� /ALD
       ������������
#
40104
4-bit 3-state bidirectional shift register with separate shift left and shift
right serial inputs.

    ����������Ŀ             �����������������������Ŀ
 OE �1  ���� 16� VCC         � S1� S0� Function      �
  D �2       15� Q3          �����������������������͵
 P3 �3       14� Q2          � 0 � 0 � Reset         �
 P2 �4       13� Q1          � 0 � 1 � Shift right   �
 P1 �5 40104 12� Q0          � 1 � 0 � Shift left    �
 P0 �6       11� CLK         � 1 � 1 � Parallel load �
  L �7       10� S1          �������������������������
GND �8        9� S0
    ������������
#
40105
16x4 3-state asynchronous FIFO with reset.

      ����������Ŀ
   OE �1  ���� 16� VCC
/FULL �2       15� RD
   WR �3       14� /EMPTY
   D0 �4       13� Q0
   D1 �5 40105 12� Q1
   D2 �6       11� Q2
   D3 �7       10� Q3
  GND �8        9� RST
      ������������
#
40106
Hex inverters with schmitt-trigger inputs.
0.9V typical input hysteresis at VCC=+5V and 2.3V at VCC=+10V.

    ����������Ŀ             �������Ŀ               _
 1A �1  ���� 14� VCC         � A �/Y �          /Y = A
/1Y �2       13� 6A          �������͵
 2A �3       12� /6Y         � 0 � 1 �
/2Y �4 40106 11� 5A          � 1 � 0 �
 3A �5       10� /5Y         ���������
/3Y �6        9� 4A
GND �7        8� /4Y
    ������������
#
40107
Dual 2-input open-collector NAND gates with buffered output.

    ����������Ŀ             �����������Ŀ           __
 1A �1  ����  8� VCC         � A � B �/Y �      /Y = AB
 1B �2        7� 2B          �����������͵
/1Y �3 40107  6� 2A          � 0 � 0 � Z �
GND �4        5� /2Y         � 0 � 1 � Z �
    ������������             � 1 � 0 � Z �
                             � 1 � 1 � 0 �
                             �������������
#
40108, 40208, 4580
4x4-bit 3-state synchronous triple-port register file.

      ��������������Ŀ
  1Q3 �1    ����   24� VCC
  1Q2 �2           23� 1Q1
  1RD �3           22� 1Q0
  2Q0 �4           21� 2RD
  2Q1 �5           20� D0
  2Q2 �6           19� D1
  2Q3 �7   40108   18� D2
  WA0 �8           17� D3
  WA1 �9           16� WCLK
 2RA1 �10          15� WR
 2RA0 �11          14� 1RA1
  GND �12          13� 1RA0
      ����������������
#
40109
Quad 3-state noninverting buffer/level shifter.
VDD

    ����������Ŀ             �������������Ŀ
VCC �1  ���� 16� VDD         � A � OE�  Y  �
1OE �2       15� 4OE         �������������͵
 1A �3       14� 4A          � X � 0 �  Z  �
 1Y �4       13� 4Y          � 0 � 1 � GND �
 2Y �5 40109 12�             � 1 � 1 � VDD �
 2A �6       11� 3Y          ���������������
2OE �7       10� 3A
GND �8        9� 3OE
    ������������
#
4011
Quad 2-input NAND gates.

    ����������Ŀ             �����������Ŀ           __
 1A �1  ���� 14� VCC         � A � B �/Y �      /Y = AB
 1B �2       13� 4B          �����������͵
/1Y �3       12� 4A          � 0 � 0 � 1 �
/2Y �4  4011 11� /4Y         � 0 � 1 � 1 �
 2A �5       10� /3Y         � 1 � 0 � 1 �
 2B �6        9� 3B          � 1 � 1 � 0 �
GND �7        8� 3A          �������������
    ������������
#
40110
4-bit asynchronous decade up/down counter with 7-segment decoder/common-
cathode LED driver, ripple carry and borrow, separate up and down clocks,
clock enable and output latch.

       ����������Ŀ
    YA �1  ���� 16� VCC
    YG �2       15� YB
    YF �3       14� YC
/CLKEN �4       13� YD
   RST �5 40110 12� YE
    LE �6       11� BORROW
 CLKDN �7       10� CARRY
   GND �8        9� CLKUP
       ������������
#
4012
Dual 4-input NAND gates.

    ����������Ŀ             �������������������Ŀ        ____
/1Y �1  ���� 14� VCC         � A � B � C � D �/Y �   /Y = ABCD
 1A �2       13� /2Y         �������������������͵
 1B �3       12� 2D          � 0 � X � X � X � 1 �
 1C �4  4012 11� 2C          � 1 � 0 � X � X � 1 �
 1D �5       10� 2B          � 1 � 1 � 0 � X � 1 �
    �6        9� 2A          � 1 � 1 � 1 � 0 � 1 �
GND �7        8�             � 1 � 1 � 1 � 1 � 0 �
    ������������             ���������������������
#
4013
Dual D flip-flop with set and reset.

      ����������Ŀ           �����������������������Ŀ
   1Q �1  ���� 14� VCC       � D �CLK�SET�RST� Q �/Q �
  /1Q �2       13� 2Q        �����������������������͵
 1CLK �3       12� /2Q       � X � X � 0 � 1 � 0 � 1 �
 1RST �4  4013 11� 2CLK      � X � X � 1 � 0 � 1 � 0 �
   1D �5       10� 2RST      � X � X � 1 � 1 � 1 � 1 �
 1SET �6        9� 2D        � 0 � / � 0 � 0 � 0 � 1 �
  GND �7        8� 2SET      � 1 � / � 0 � 0 � 1 � 1 �
      ������������           � X �!/ � 0 � 0 � - � - �
                             �������������������������
#
4014
8-bit parallel-in serial-out shift register with three parallel outputs.

    ����������Ŀ
 P0 �1  ���� 16� VCC
 Q2 �2       15� P1
 Q0 �3       14� P2
 P4 �4       13� P3
 P5 �5  4014 12� Q1
 P6 �6       11� D
 P7 �7       10� CLK
GND �8        9� LD//SH
    ������������
#
40147
10-to-4 line noninverting priority encoder.

    ����������Ŀ
 A4 �1  ���� 16� VCC
 A5 �2       15� A0
 A6 �3       14� Y3
 A7 �4       13� A3
 A8 �5 40147 12� A2
 Y2 �6       11� A1
 Y1 �7       10� A9
GND �8        9� Y0
    ������������
#
4015, 744015
Dual 4-bit serial-in parallel-out shift register with asynchronous reset.

     ����������Ŀ
2CLK �1  ���� 16� VCC
 2Q0 �2       15� 2D
 1Q1 �3       14� 2RST
 1Q2 �4       13� 2Q3
 1Q3 �5  4015 12� 2Q2
1RST �6       11� 2Q1
  1D �7       10� 1Q0
 GND �8        9� 1CLK
     ������������
#
4016, 4066, 744016, 744066
Quad analog switches.

     ����������Ŀ
  1X �1  ���� 14� VCC
  1Y �2       13� 1EN
  2Y �3       12� 4EN
  2X �4  4016 11� 4X
 2EN �5  4066 10� 4Y
 3EN �6        9� 3Y
 GND �7        8� 3X
     ������������
#
4017, 744017
4-bit asynchronous decade counter with fully decoded outputs, reset and both
active high and active low clocks.

    ����������Ŀ
 Q5 �1  ���� 16� VCC
 Q1 �2       15� RST
 Q0 �3       14� CLK1
 Q2 �4       13� /CLK2
 Q6 �5  4017 12� RCO
 Q7 �6       11� Q9
 Q3 �7       10� Q4
GND �8        9� Q8
    ������������
#
4018
5-stage (divide by 2,4,6,8 or 10) Johnson counter with preset inputs.

    ����������Ŀ
  D �1  ���� 16� VCC
 P1 �2       15� RST
 P2 �3       14� CLK
/Q2 �4       13� /Q5
/Q1 �5  4018 12� P5
/Q3 �6       11� /Q4
 P3 �7       10� PE
GND �8        9� P4
    ������������
#
4019
8-to-4 line noninverting data selector/multiplexer with OR function.

    ����������Ŀ             �������������������Ŀ
4A1 �1  ���� 16� VCC         � A0� A1� S1� S0� Y �    Y=S0�A0+S1�A1
3A0 �2       15� 4A0         �������������������͵
3A1 �3       14� S1          � X � X � 0 � 0 � 0 �
2A0 �4       13� Y4          � X � 0 � 0 � 1 � 0 �
2A1 �5  4019 12� Y3          � 0 � X � 1 � 0 � 0 �
1A0 �6       11� Y2          � X � 1 � X � 1 � 1 �
1A1 �7       10� Y1          � 1 � X � 1 � X � 1 �
GND �8        9� S0          ���������������������
    ������������
#
40194
4-bit bidirectional shift register with asynchronous reset and separate
shift left and shift right serial inputs.

     ����������Ŀ            �����������������������Ŀ
/RST �1  ���� 16� VCC        � S1� S0� Function      �
   D �2       15� Q3         �����������������������͵
  P3 �3       14� Q2         � 0 � 0 � Hold          �
  P2 �4       13� Q1         � 0 � 1 � Shift right   �
  P1 �5 40194 12� Q0         � 1 � 0 � Shift left    �
  P0 �6       11� CLK        � 1 � 1 � Parallel load �
   L �7       10� S1         �������������������������
 GND �8        9� S0
     ������������
#
4020, 744020
14-bit asynchronous binary counter with reset.
Q1 and Q2 outputs missing.

    ����������Ŀ
Q11 �1  ���� 16� VCC
Q12 �2       15� Q10
Q13 �3       14� Q9
 Q5 �4       13� Q7
 Q4 �5  4020 12� Q8
 Q6 �6       11� RST
 Q3 �7       10� /CLK
GND �8        9� Q0
    ������������
#
4021
8-bit parallel-in serial-out shift register with asynchronous load input
and three parallel outputs.

    ����������Ŀ
 P0 �1  ���� 16� VCC
 Q2 �2       15� P1
 Q0 �3       14� P2
 P4 �4       13� P3
 P5 �5  4021 12� Q1
 P6 �6       11� D
 P7 �7       10� CLK
GND �8        9� LD//SH
    ������������
#
4022
3-bit asynchronous binary counter with fully decoded outputs, reset and both
active high and active low clocks.

    ����������Ŀ
 Q1 �1  ���� 16� VCC
 Q0 �2       15� RST
 Q2 �3       14� CLK1
 Q5 �4       13� /CLK2
 Q6 �5  4022 12� RCO
    �6       11� Q4
 Q3 �7       10� Q7
GND �8        9�
    ������������
#
4023
Triple 3-input NAND gates.

    ����������Ŀ             ���������������Ŀ       ___
 1A �1  ���� 14� VCC         � A � B � C �/Y �  /Y = ABC
 1B �2       13� 3C          ���������������͵
 2A �3       12� 3B          � 0 � X � X � 1 �
 2B �4  4023 11� 3A          � 1 � 0 � X � 1 �
 2C �5       10� /3Y         � 1 � 1 � 0 � 1 �
/2Y �6        9� /1Y         � 1 � 1 � 1 � 0 �
GND �7        8� 1C          �����������������
    ������������
#
4024, 744024
7-bit asynchronous binary counter with reset.

     ����������Ŀ
/CLK �1  ���� 14� VCC
 RST �2       13�
  Q6 �3       12� Q0
  Q5 �4  4024 11� Q1
  Q4 �5       10�
  Q3 �6        9� Q2
 GND �7        8�
     ������������
#
4025
Triple 3-input NOR gates.

    ����������Ŀ             ���������������Ŀ       _____
 1A �1  ���� 14� VCC         � A � B � C �/Y �  /Y = A+B+C
 1B �2       13� 3C          ���������������͵
 2A �3       12� 3B          � 0 � 0 � 0 � 1 �
 2B �4  4025 11� 3A          � 0 � 0 � 1 � 0 �
 2C �5       10� /3Y         � 0 � 1 � X � 0 �
/2Y �6        9� /1Y         � 1 � X � X � 0 �
GND �7        8� 1C          �����������������
    ������������
#
4026
4-bit asynchronous decade counter with 7-segment decoder, display enable,
ripple carry, reset and both active high and active low clocks.

      ����������Ŀ
 CLK1 �1  ���� 16� VCC
/CLK2 �2       15� RST
  DEI �3       14� YC'
  DEO �4       13� YC
   CO �5  4026 12� YB
   YF �6       11� YE
   YG �7       10� YA
  GND �8        9� YD
      ������������
#
4027
Dual J-K flip-flops with set and reset.

      ����������Ŀ           ���������������������������Ŀ
   1Q �1  ���� 16� VCC       � J � K �CLK�SET�RST� Q �/Q �
  /1Q �2       15� 2Q        ���������������������������͵
 1CLK �3       14� /2Q       � X � X � X � 1 � 1 � 1 � 1 �
 1RST �4       13� 2CLK      � X � X � X � 1 � 0 � 1 � 0 �
   1K �5  4027 12� 2RST      � X � X � X � 0 � 1 � 0 � 1 �
   1J �6       11� 2K        � 0 � 0 � / � 0 � 0 � - � - �
 1SET �7       10� 2J        � 0 � 1 � / � 0 � 0 � 0 � 1 �
  GND �8        9� 2SET      � 1 � 0 � / � 0 � 0 � 1 � 0 �
      ������������           � 1 � 1 � / � 0 � 0 �/Q � Q �
                             � X � X �!/ � 0 � 0 � - � - �
                             �����������������������������
#
4028
1-of-10 noninverting decoder/demultiplexer.

    ����������Ŀ             �������������������������������Ŀ
 Y4 �1  ���� 16� VCC         � S3� S2� S1� S0� Y0� Y1�...� Y9�
 Y2 �2       15� Y3          �������������������������������͵
 Y0 �3       14� Y1          � 0 � 0 � 0 � 0 � 1 � 0 � 0 � 0 �
 Y7 �4       13� S1          � 0 � 0 � 0 � 1 � 0 � 1 � 0 � 0 �
 Y9 �5  4028 12� S2          � . � . � . � . � 0 � 0 � . � 0 �
 Y5 �6       11� S3          � 1 � 0 � 0 � 1 � 0 � 0 � 0 � 1 �
 Y6 �7       10� S0          � 1 � 0 � 1 � X � 0 � 0 � 0 � 0 �
GND �8        9� Y8          � 1 � 1 � X � X � 0 � 0 � 0 � 0 �
    ������������             ���������������������������������
#
4029
4-bit synchronous binary/decade up/down counter with preset and ripple carry
output.

     ����������Ŀ
  PE �1  ���� 16� VCC
  Q4 �2       15� CLK
  P4 �3       14� Q3
  P1 �4       13� P3
/RCI �5  4029 12� P2
  Q1 �6       11� Q2
/RCO �7       10� U//D
 GND �8        9� B//D
     ������������
#
4030
Quad 2-input XOR gates.

    ����������Ŀ             �����������Ŀ                    _   _
 1A �1  ���� 14� VCC         � A � B � Y �       Y = A$B = (A�B)+(A�B)
 1B �2       13� 4B          �����������͵
 1Y �3       12� 4A          � 0 � 0 � 0 �
 2Y �4  4030 11� 4Y          � 0 � 1 � 1 �
 2A �5       10� 3Y          � 1 � 0 � 1 �
 2B �6        9� 3B          � 1 � 1 � 0 �
GND �7        8� 3A          �������������
    ������������
#
4031
64-bit serial-in serial-out shift register.
S selects between D (when 0) and E serial inputs.  Y is Q delayed by half a
cycle (i.e. clocked on falling edge).

    ����������Ŀ
  E �1  ���� 16� VCC
CLK �2       15� D
    �3       14�
    �4       13�
  Y �5  4031 12�
  Q �6       11�
 /Q �7       10� S
GND �8        9� CLKout
    ������������
#
4032
Triple serial adder.
Each section can be used to add long binary words, one bit on each clock
cycle.  CRST resets the internal carry flip-flop after one clock delay.
The INV inputs can be used to invert the sum output (giving a 1's-complemented
result).

     ����������Ŀ
  3� �1  ���� 16� VCC
3INV �2       15� 3A
 CLK �3       14� 3B
  2� �4       13� 2A
2INV �5  4032 12� 2B
CRST �6       11� 1B
1INV �7       10� 1A
 GND �8        9� 1�
     ������������
#
4033
4-bit asynchronous decade counter with 7-segment decoder, ripple blanking,
ripple carry, reset and both active high and active low clocks.

      ����������Ŀ
 CLK1 �1  ���� 16� VCC
/CLK2 �2       15� RST
  RBI �3       14� LT
  RBO �4       13� YC
   CO �5  4033 12� YB
   YF �6       11� YE
   YG �7       10� YA
  GND �8        9� YD
      ������������
#
4034
8-bit bidirectional shift register with dual parallel I/O ports
and selectable synchronous/asynchronous parallel load.

     ��������������Ŀ
  A0 �1    ����   24� VCC
  A1 �2           23� B0
  A2 �3           22� B1
  A3 �4           21� B2
  A4 �5           20� B3
  A5 �6           19� B4
  A6 �7    4034   18� B5
  A7 �8           17� B6
 ENA �9           16� B7
   D �10          15� CLK
B//A �11          14� SY//ASY
 GND �12          13� LD//SH
     ����������������
#
4035
4-bit inverting/noninverting shift register with J-/K inputs and
asynchronous reset.

       ����������Ŀ
    Q3 �1  ���� 16� VCC
  /INV �2       15� Q2
    /K �3       14� Q1
     J �4       13� Q0
   RST �5  4035 12� P0
   CLK �6       11� P1
LD//SH �7       10� P2
   GND �8        9� P3
       ������������
#
4038
Triple negative-edge-triggered serial adder.
Each section can be used to add long binary words, one bit on each clock
cycle.  CRST resets the internal carry flip-flop after one clock delay.
The INV inputs can be used to invert the sum output (giving a 1's-complemented
result).

     ����������Ŀ
  3� �1  ���� 16� VCC
3INV �2       15� 3A
/CLK �3       14� 3B
  2� �4       13� 2A
2INV �5  4038 12� 2B
CRST �6       11� 1B
1INV �7       10� 1A
 GND �8        9� 1�
     ������������
#
4040, 744040
12-bit asynchronous binary counter with reset.

    ����������Ŀ
Q11 �1  ���� 16� VCC
 Q5 �2       15� Q10
 Q4 �3       14� Q9
 Q6 �4       13� Q7
 Q3 �5  4040 12� Q8
 Q2 �6       11� RST
 Q1 �7       10� /CLK
GND �8        9� Q0
    ������������
#
4041
Quad buffers with complementary outputs.

    ����������Ŀ             �����������Ŀ
 1Y �1  ���� 14� VCC         � A � Y �/Y �       Y = A
/1Y �2       13� 4A          �����������͵
 1A �3       12� /4Y         � 0 � 0 � 1 �
 2Y �4  4041 11� 4Y          � 1 � 1 � 0 �
/2Y �5       10� 3A          �������������
 2A �6        9� /3Y
GND �7        8� 3Y
    ������������
#
4042
4-bit transparent latch with selectable latch enable polarity and
complementary outputs.

    ����������Ŀ             �������������������Ŀ
 Q3 �1  ���� 16� VCC         � LE� LP� D � Q �/Q �
 Q0 �2       15� /Q3         �������������������͵
/Q0 �3       14� D3          � 0 � 0 � 0 � 0 � 1 �
 D0 �4       13� D2          � 0 � 0 � 1 � 1 � 0 �
 LE �5  4042 12� /Q2         � 1 � 0 � X � - � - �
 LP �6       11� Q2          � 1 � 1 � 0 � 0 � 1 �
 D2 �7       10� Q1          � 1 � 1 � 1 � 1 � 0 �
GND �8        9� /Q1         � 0 � 1 � X � - � - �
    ������������             ���������������������
#
4043
Quad 3-state S-R latches with overriding set.

    ����������Ŀ             ���������������Ŀ
 1Q �1  ���� 16� VCC         � S � R � OE� Q �
 2Q �2       15� 1R          ���������������͵
 2R �3       14� 1S          � X � X � 0 � Z �
 2S �4       13�             � 0 � 0 � 1 � - �
 OE �5  4043 12� 4S          � 0 � 1 � 1 � 1 �
 3S �6       11� 4R          � 1 � 0 � 1 � 0 �
 3R �7       10� 4Q          � 1 � 1 � 1 � 1 �
GND �8        9� 3Q          �����������������
    ������������
#
4044
Quad 3-state S-R latches with overriding reset.

    ����������Ŀ             ���������������Ŀ
 1Q �1  ���� 16� VCC         � S � R � OE� Q �
    �2       15� 4S          ���������������͵
 2S �3       14� 4R          � X � X � 0 � Z �
 2R �4       13� 2Q          � 0 � 0 � 1 � - �
 OE �5  4044 12� 4R          � 0 � 1 � 1 � 1 �
 3S �6       11� 4S          � 1 � 0 � 1 � 0 �
 3R �7       10� 4Q          � 1 � 1 � 1 � 0 �
GND �8        9� 3Q          �����������������
    ������������
#
4045
21-bit asynchronous binary counter with oscillator and reset input.
Only two 3% duty cycle outputs (180� out of phase) from the last counter stage
are available.  Can be used to generate a 1Hz clock signal using a 2.097152MHz
crystal.  P and N MOSFET source connections from the oscillator inverter are
brought out of the package to allow the use of source resistors, but usually
pS=VCC and nS=GND.

    ����������Ŀ
 pS �1  ���� 16� X1
 nS �2       15� X0
VCC �3       14� GND
    �4       13�
    �5  4045 12�
    �6       11�
 QA �7       10�
 QB �8        9�
    ������������
#
4046, 744046
Phase Locked Loop.

       ����������Ŀ
PCPout �1  ���� 16� VCC
PC1out �2       15� Zener
 PCinB �3       14� PCinA
VCOout �4       13� PC2out
   /EN �5  4046 12� R2
   C1A �6       11� R1
   C1B �7       10� SFout
   GND �8        9� VCOin
       ������������
#
4047
Low-power astable/monostable multivibrator with oscillator output.

      ����������Ŀ
 Cext �1  ���� 14� VCC
 Rext �2       13� OSC
RCext �3       12� RETRIG
 /AST �4  4047 11� /Q
  AST �5       10� Q
  /TR �6        9� RST
  GND �7        8� TR
      ������������
#
4048
3-state 8-input multifunction gate.

    ����������Ŀ             ����������������������������������������Ŀ
  Y �1  ���� 16� VCC         � S2� S1� S0� OE� Output function        �
 OE �2       15� X           ����������������������������������������͵
  A �3       14� H           � X � X � X � 0 � Z                      �
  B �4       13� G           � 0 � 0 � 0 � 1 � 8-input NOR            �
  C �5  4048 12� F           � 0 � 0 � 1 � 1 � 8-input OR             �
  D �6       11� E           � 0 � 1 � 0 � 1 � 2-wide 4-input OR-AND  �
 S1 �7       10� S2          � 0 � 1 � 1 � 1 � 2-wide 4-input OR-NAND �
GND �8        9� S0          � 1 � 0 � 0 � 1 � 8-input AND            �
    ������������             � 1 � 0 � 1 � 1 � 8-input NAND           �
                             � 1 � 1 � 0 � 1 � 2-wide 4-input AND-NOR �
                             � 1 � 1 � 1 � 1 � 2-wide 4-input AND-OR  �
                             ������������������������������������������
#
4049, 744049
Hex inverters with high-to-low level shifter inputs.

    ����������Ŀ             �������Ŀ               _
VCC �1  ���� 16�             � A �/Y �          /Y = A
/Y1 �2       15� /Y6         �������͵
 A1 �3       14� A6          � 0 � 1 �
/Y2 �4       13�             � 1 � 0 �
 A2 �5  4049 12� /Y5         ���������
/Y3 �6       11� A5
 A3 �7       10� /Y4
GND �8        9� A4
    ������������
#
4050, 744050
Hex buffers with high-to-low level shifter inputs.

    ����������Ŀ             �������Ŀ
VCC �1  ���� 16�             � A � Y �           Y = A
 Y1 �2       15� Y6          �������͵
 A1 �3       14� A6          � 0 � 0 �
 Y2 �4       13�             � 1 � 1 �
 A2 �5  4050 12� Y5          ���������
 Y3 �6       11� A5
 A3 �7       10� Y4
GND �8        9� A4
    ������������
#
4051, 744051
8-to-1 line analog multiplexer/demultiplexer with dual power supply.
VEE supply may not be more positive than GND.

    ����������Ŀ
 X4 �1  ���� 16� VCC
 X6 �2       15� X2
  Y �3       14� X1
 X7 �4       13� X0
 X5 �5  4051 12� X3
/EN �6       11� S0
VEE �7       10� S1
GND �8        9� S2
    ������������
#
4052, 744052
8-to-2 line analog multiplexer/demultiplexer with dual power supply.
VEE supply may not be more positive than GND.

    ����������Ŀ
1X0 �1  ���� 16� VCC
1X2 �2       15� 2X2
 1Y �3       14� 2X1
1X3 �4       13� 2Y
1X1 �5  4052 12� 2X0
/EN �6       11� 2X3
VEE �7       10� S0
GND �8        9� S1
    ������������
#
4053, 744053
Triple 2-to-1 line analog multiplexer/demultiplexer with dual power supply.
VEE supply may not be more positive than GND.

    ����������Ŀ
1X0 �1  ���� 16� VCC
1X1 �2       15� 1Y
2X1 �3       14� 3Y
 2Y �4       13� 3X1
2X0 �5  4053 12� 3X0
/EN �6       11� 3S
VEE �7       10� 1S
GND �8        9� 2S
    ������������
#
4054
Quad level shifters/LCD drivers with input latches.
A level-shifted inverse of the � (phase) input should be connected to the
backplane of the LCD; this can be done by using one section of the 4054
with A=0 and LE=1.

    ����������Ŀ             �����������Ŀ            _ 
1LE �1  ���� 16� VCC         � LE� A � R �       Y = R$�
  � �2       15� 1A          �����������͵
 1Y �3       14� 2LE         � 0 � X � - �
 2Y �4       13� 2A          � 1 � 0 � 0 �
 3Y �5  4054 12� 3LE         � 1 � 1 � 1 �
 4Y �6       11� 3A          �������������
VEE �7       10� 4LE
GND �8        9� 4A
    ������������
#
4055
BCD to 7-segment decoder/LCD driver.
The �o (phase) output should be connected to the backplane of the LCD.

    ����������Ŀ
 �o �1  ���� 16� VCC
 A2 �2       15� YF
 A1 �3       14� YG
 A3 �4       13� YE
 A0 �5  4055 12� YD
 �i �6       11� YC
VEE �7       10� YB
GND �8        9� YA
    ������������
#
4056
BCD to 7-segment decoder/LCD driver with input latches.
A level-shifted inverse of the � (phase) input should be connected to the
backplane of the LCD.

    ����������Ŀ
 LE �1  ���� 16� VCC
 A2 �2       15� YF
 A1 �3       14� YG
 A3 �4       13� YE
 A0 �5  4056 12� YD
  � �6       11� YC
VEE �7       10� YB
GND �8        9� YA
    ������������
#
4059
Divide by N counter.
Ka, Kb, Kc are the modulus (divide by number) of the 1st and last
counting sections. N can range from 3 to 15999.  The down-counter
is preset by 15 jam inputs.

    ��������������Ŀ
CLK �1    ����   24� VCC
 LD �2           23� Q
 J1 �3           22� J5
 J2 �4           21� J6
 J3 �5           20� J7
 J4 �6           19� J8
J16 �7    4059   18� J9
J15 �8           17� J10
J14 �9           16� J11
J13 �10          15� J12
 Kc �11          14� Ka
GND �12          13� Kb
    ����������������
#
4060, 744060
14-bit asynchronous binary counter with oscillator and reset input.
Q0,Q1,Q2 and Q10 outputs are missing.

    ����������Ŀ
Q11 �1  ���� 16� VCC
Q12 �2       15� Q9
Q13 �3       14� Q7
 Q5 �4       13� Q8
 Q4 �5  4060 12� RST
 Q6 �6       11� X1
 Q3 �7       10� X0
GND �8        9� X2
    ������������
#
4063
4-bit noninverting magnitude comparator with cascade inputs.

     ����������Ŀ
  B3 �1  ���� 16� VCC
IAB �4       13� A2
OA>B �5  4063 12� A1
OA=B �6       11� B1
OA10k� resistor to ground for square wave output,
or to a RC network (R to VCC) for a controlled output pulse width.
Maximum guaranteed clock frequency is 500kHz at VCC=+5V (what a pity!!!).

        ����������Ŀ
    SET �1  ���� 16� VCC
    RST �2       15� MONO
     X1 �3       14� /XEN
     X0 �4       13� Q
     X2 �5  4536 12� S3
/DIV256 �6       11� S2
  CLKEN �7       10� S1
    GND �8        9� S0
        ������������
#
4538, 744538
Dual precision monostable multivibrator with Schmitt-trigger inputs.
Retriggerable, resettable.
For 74HC4538 the Cext pin may be grounded.

       ����������Ŀ
 1Cext �1  ���� 16� VCC
1RCext �2       15� 2Cext
  1RST �3       14� 2RCext
   1TR �4       13� 2RST
  /1TR �5  4538 12� 2TR
    1Q �6       11� /2TR
   /1Q �7       10� 2Q
   GND �8        9� /2Q
       ������������
#
4543, 744543
BCD to 7-segment decoder/LCD driver with input latch.
The � (phase) input should be connected to the backplane of the LCD.

    ����������Ŀ
 LE �1  ���� 16� VCC
 A2 �2       15� YF
 A1 �3       14� YG
 A3 �4       13� YE
 A0 �5  4543 12� YD
  � �6       11� YC
 BI �7       10� YB
GND �8        9� YA
    ������������
#
4555
Dual 1-of-4 noninverting decoder/demultiplexer.

     ����������Ŀ            ���������������������������Ŀ
/1EN �1  ���� 16� VCC        �/EN� S1� S0� Y0� Y1� Y2� Y3�
 1S0 �2       15� /2EN       ���������������������������͵
 1S1 �3       14� 2S0        � 1 � X � X � 0 � 0 � 0 � 0 �
 1Y0 �4       13� 2S1        � 0 � 0 � 0 � 1 � 0 � 0 � 0 �
 1Y1 �5  4555 12� 2Y0        � 0 � 0 � 1 � 0 � 1 � 0 � 0 �
 1Y2 �6       11� 2Y1        � 0 � 1 � 0 � 0 � 0 � 1 � 0 �
 1Y3 �7       10� 2Y2        � 0 � 1 � 1 � 0 � 0 � 0 � 1 �
 GND �8        9� 2Y3        �����������������������������
     ������������
#
4556
Dual 1-of-4 inverting decoder/demultiplexer.

     ����������Ŀ            ���������������������������Ŀ
/1EN �1  ���� 16� VCC        �/EN� S1� S0�/Y0�/Y1�/Y2�/Y3�
 1S0 �2       15� /2EN       ���������������������������͵
 1S1 �3       14� 2S0        � 1 � X � X � 1 � 1 � 1 � 1 �
/1Y0 �4       13� 2S1        � 0 � 0 � 0 � 0 � 1 � 1 � 1 �
/1Y1 �5  4556 12� /2Y0       � 0 � 0 � 1 � 1 � 0 � 1 � 1 �
/1Y2 �6       11� /2Y1       � 0 � 1 � 0 � 1 � 1 � 0 � 1 �
/1Y3 �7       10� /2Y2       � 0 � 1 � 1 � 1 � 1 � 1 � 0 �
 GND �8        9� /2Y3       �����������������������������
     ������������
#
4585
4-bit noninverting magnitude comparator with cascade inputs.

     ����������Ŀ
  B2 �1  ���� 16� VCC
  A2 �2       15� A3
OA=B �3       14� B3
IA>B �4       13� OA>B
IAB �1  ���� 20� VCC
  A0 �2       19� A=B
  B0 �3       18� B7
  A1 �4       17� A7
  B1 �5   74  16� B6
  A2 �6  682  15� A6
  B2 �7       14� B5
  A3 �8       13� A5
  B3 �9       12� B4
 GND �10      11� A4
     ������������
#
74684
8-bit inverting magnitude comparator.

     ����������Ŀ
/A>B �1  ���� 20� VCC
  A0 �2       19� A=B
  B0 �3       18� B7
  A1 �4       17� A7
  B1 �5   74  16� B6
  A2 �6  684  15� A6
  B2 �7       14� B5
  A3 �8       13� A5
  B3 �9       12� B4
 GND �10      11� A4
     ������������
#
74686
8-bit inverting magnitude comparator with enable.

     ����������Ŀ
/A>B �1  ���� 24� VCC
/EN1 �2       23� /EN2
  A0 �3       22� /A=B
  B0 �4       21� B7
  A1 �5       20� A7
  B1 �6   74  19�
     �7  686  18� B6
  A2 �8       17� A6
  B2 �9       16� B5
  A3 �10      15� A5
  B3 �11      14� B4
 GND �12      13� A4
     ������������
#
74687
8-bit open-collector inverting magnitude comparator with enable.

     ����������Ŀ
/A>B �1  ���� 24� VCC
/EN1 �2       23� /EN2
  A0 �3       22� /A=B
  B0 �4       21� B7
  A1 �5       20� A7
  B1 �6   74  19�
     �7  687  18� B6
  A2 �8       17� A6
  B2 �9       16� B5
  A3 �10      15� A5
  B3 �11      14� B4
 GND �12      13� A4
     ������������
#
74688
8-bit inverting identity comparator with enable.

    ����������Ŀ
/EN �1  ���� 20� VCC
 A0 �2       19� A=B
 B0 �3       18� B7
 A1 �4       17� A7
 B1 �5   74  16� B6
 A2 �6  688  15� A6
 B2 �7       14� B5
 A3 �8       13� A5
 B3 �9       12� B4
GND �10      11� A4
    ������������
#
74689
8-bit open-collector inverting identity comparator with enable.

    ����������Ŀ
/EN �1  ���� 20� VCC
 A0 �2       19� A=B
 B0 �3       18� B7
 A1 �4       17� A7
 B1 �5   74  16� B6
 A2 �6  689  15� A6
 B2 �7       14� B5
 A3 �8       13� A5
 B3 �9       12� B4
GND �10      11� A4
    ������������
#
74691
4-bit 3-state synchronous binary counter with output registers, asynchronous
reset and ripple carry output.  Multiplexed register/counter outputs.

      ����������Ŀ
/CRST �1  ���� 20� VCC
 CCLK �2       19� RCO
   P0 �3       18� Q0
   P1 �4       17� Q1
   P2 �5   74  16� Q2
   P3 �6  691  15� Q3
  ENP �7       14� ENT
/RRST �8       13� /LOAD
 RCLK �9       12� /OE
  GND �10      11� R//C
      ������������
#
74697
4-bit 3-state synchronous binary up/down counter with output registers,
asynchronous reset and ripple carry output.  Multiplexed register/counter
outputs.

      ����������Ŀ
 U//D �1  ���� 20� VCC
 CCLK �2       19� RCO
   P0 �3       18� Q0
   P1 �4       17� Q1
   P2 �5   74  16� Q2
   P3 �6  697  15� Q3
  ENP �7       14� ENT
/CRST �8       13� /LOAD
 RCLK �9       12� /OE
  GND �10      11� R//C
      ������������
#
74699
4-bit 3-state synchronous binary up/down counter with output registers,
reset and ripple carry output.  Multiplexed register/counter
outputs.

      ����������Ŀ
 U//D �1  ���� 20� VCC
 CCLK �2       19� RCO
   P0 �3       18� Q0
   P1 �4       17� Q1
   P2 �5   74  16� Q2
   P3 �6  699  15� Q3
  ENP �7       14� ENT
/CRST �8       13� /LOAD
 RCLK �9       12� /OE
  GND �10      11� R//C
      ������������
#
747001
Quad 2-input AND gates with schmitt-trigger inputs.
0.8V typical input hysteresis at VCC=+5V.

    ����������Ŀ             �����������Ŀ
 1A �1  ���� 14� VCC         � A � B � Y �       Y = AB
 1B �2       13� 4B          �����������͵
 1Y �3  747  12� 4A          � 0 � 0 � 0 �
 2A �4  001  11� 4Y          � 0 � 1 � 0 �
 2B �5       10� 3B          � 1 � 0 � 0 �
 2Y �6        9� 3A          � 1 � 1 � 1 �
GND �7        8� 3Y          �������������
    ������������
#
7472
J-K flip-flop with triple ANDed J an K inputs, set and reset.

     ����������Ŀ            ���������������������������������������Ŀ
     �1  ���� 14� VCC        �J1�J2�J3�K1�K2�K3�CLK�/SET�/RST� Q �/Q �
/RST �2       13� /SET       ���������������������������������������͵
  J1 �3       12� CLK        �    X   �    X   � X �  0 �  0 � ? � ? �
  J2 �4  7472 11� K3         �    X   �    X   � X �  0 �  1 � 1 � 0 �
  J3 �5       10� K2         �    X   �    X   � X �  1 �  0 � 0 � 1 �
  /Q �6        9� K1         �    0   �    0   � / �  1 �  1 � - � - �
 GND �7        8� Q          �    0   �    1   � / �  1 �  1 � 0 � 1 �
     ������������            �    1   �    0   � / �  1 �  1 � 1 � 0 �
                             �    1   �    1   � / �  1 �  1 �/Q � Q �
                             �    X   �    X   �!/ �  1 �  1 � - � - �
                             �����������������������������������������
#
747266
Quad 2-input XNOR gates.

    ����������Ŀ             �����������Ŀ           _ 
 1A �1  ���� 14� VCC         � A � B �/Y �     /Y = A$B
 1B �2       13� 4B          �����������͵
/1Y �3  747  12� 4A          � 0 � 0 � 1 �
 2A �4  266  11� /4Y         � 0 � 1 � 0 �
 2B �5       10� 3B          � 1 � 0 � 0 �
/2Y �6        9� 3A          � 1 � 1 � 1 �
GND �7        8� /3Y         �������������
    ������������
#
7473
Dual negative-edge-triggered J-K flip-flop with reset.

      ����������Ŀ           �������������������������Ŀ
/1CLK �1  ���� 14� 1J        � J � K �/CLK�/RST� Q �/Q �
/1RST �2       13� /1Q       �������������������������͵
   1K �3       12� 1Q        � X � X �  X �  0 � 0 � 1 �
  VCC �4  7473 11� GND       � 0 � 0 �  \ �  1 � - � - �
/2CLK �5       10� 2K        � 0 � 1 �  \ �  1 � 0 � 1 �
/2RST �6        9� 2Q        � 1 � 0 �  \ �  1 � 1 � 0 �
   2J �7        8� /2Q       � 1 � 1 �  \ �  1 �/Q � Q �
      ������������           � X � X � !\ �  1 � - � - �
                             ���������������������������
#
7474
Dual D flip-flop with set and reset.

      ����������Ŀ           �������������������������Ŀ
/1RST �1  ���� 14� VCC       � D �CLK�/SET�/RST� Q �/Q �
   1D �2       13� /2RST     �������������������������͵
 1CLK �3       12� 2D        � X � X �  0 �  0 � 1 � 1 �
/1SET �4  7474 11� 2CLK      � X � X �  0 �  1 � 1 � 0 �
   1Q �5       10� /2SET     � X � X �  1 �  0 � 0 � 1 �
  /1Q �6        9� 2Q        � 0 � / �  1 �  1 � 0 � 1 �
  GND �7        8� /2Q       � 1 � / �  1 �  1 � 1 � 1 �
      ������������           � X �!/ �  1 �  1 � - � - �
                             ���������������������������
#
7475
Dual 2-bit transparent latches with complementary outputs.

     ����������Ŀ
/1Q1 �1  ���� 16� 1Q1
 1D1 �2       15� 1Q2
 1D2 �3       14� /1Q2
 2LE �4       13� 1LE
 VCC �5  7475 12� GND
 2D1 �6       11� /2Q1
 2D2 �7       10� 2Q1
/2Q2 �8        9� 2Q2
     ������������
#
74756
Dual 4-bit open-collector inverting buffer/line driver.

     ����������Ŀ
/1OE �1  ���� 20� VCC
 1A1 �2       19� /2OE
/2Y4 �3       18� /1Y1
 1A2 �4       17� 2A4
/2Y3 �5  74   16� /1Y2
 1A3 �6  756  15� 2A3
/2Y2 �7       14� /1Y3
 1A4 �8       13� 2A2
/2Y1 �9       12� /1Y4
 GND �10      11� 2A1
     ������������
#
74757
Dual 4-bit open-collector noninverting buffer/line driver.
One active low, one active high output enable.

     ����������Ŀ
/1OE �1  ���� 20� VCC
 1A4 �2       19� 2OE
 2Y1 �3       18� 1Y1
 1A3 �4       17� 2A4
 2Y2 �5  74   16� 1Y2
 1A2 �6  757  15� 2A3
 2Y3 �7       14� 1Y3
 1A1 �8       13� 2A2
 2Y4 �9       12� 1Y4
 GND �10      11� 2A1
     ������������
#
74758
4-bit open-collector inverting bus transceiver.
Two enable pins control output enables, one active high and one active low.

     ����������Ŀ
/GAB �1  ���� 14� VCC
     �2       13� GBA
  A1 �3  74   12�
  A2 �4  758  11� B1
  A3 �5       10� B2
  A4 �6        9� B3
 GND �7        8� B4
     ������������
#
7476
Dual J-K flip-flops with set and reset.

      ����������Ŀ           �����������������������������Ŀ
 1CLK �1  ���� 16� 1K        � J � K �CLK�/SET�/RST� Q �/Q �
/1SET �2       15� 1Q        �����������������������������͵
/1RST �3       14� /1Q       � X � X � X �  0 �  0 � 0 � 0 �
   1J �4       13� GND       � X � X � X �  0 �  1 � 1 � 0 �
  VCC �5  7476 12� K         � X � X � X �  1 �  0 � 0 � 1 �
 2CLK �6       11� 2Q        � 0 � 0 � / �  1 �  1 � - � - �
/2SET �7       10� /2Q       � 0 � 1 � / �  1 �  1 � 0 � 1 �
/2RST �8        9� 2J        � 1 � 0 � / �  1 �  1 � 1 � 0 �
      ������������           � 1 � 1 � / �  1 �  1 �/Q � Q �
                             � X � X �!/ �  1 �  1 � - � - �
                             �������������������������������
#
74760
Dual 4-bit open-collector noninverting buffer/line driver.

     ����������Ŀ
/1OE �1  ���� 20� VCC
 1A1 �2       19� /2OE
 2Y4 �3       18� 1Y1
 1A2 �4       17� 2A4
 2Y3 �5  74   16� 1Y2
 1A3 �6  760  15� 2A3
 2Y2 �7       14� 1Y3
 1A4 �8       13� 2A2
 2Y1 �9       12� 1Y4
 GND �10      11� 2A1
     ������������
#
7478
Dual negative-edge-triggered J-K flip-flops with common clock, set and
common reset.

      ����������Ŀ           ������������������������������Ŀ
 /CLK �1  ���� 14� 1K        � J � K �/CLK�/SET�/RST� Q �/Q �
/1SET �2       13� 1Q        ������������������������������͵
   1J �3       12� /1Q       � X � X �  X �  0 �  0 � ? � ? �
  VCC �4  7478 11� GND       � X � X �  X �  0 �  1 � 1 � 0 �
 /RST �5       10� 2J        � X � X �  X �  1 �  0 � 0 � 1 �
/2SET �6        9� /2Q       � 0 � 0 �  \ �  1 �  1 � - � - �
   2K �7        8� 2Q        � 0 � 1 �  \ �  1 �  1 � 0 � 1 �
      ������������           � 1 � 0 �  \ �  1 �  1 � 1 � 0 �
                             � 1 � 1 �  \ �  1 �  1 �/Q � Q �
                             � X � X � !\ �  1 �  1 � - � - �
                             ��������������������������������
#
748003
Dual 2-input NAND gates.

    ����������Ŀ                 __
 1A �1  ����  8� VCC        /Y = AB
 1B �2  748   7� 2B
/1Y �3  003   6� 2A
GND �4        5� /2Y
    ������������

#
74804
Hex 2-input NAND gates/line drivers.

    ����������Ŀ             �����������Ŀ           __
 1A �1  ���� 20� VCC         � A � B �/Y �      /Y = AB
 1B �2       19� 6B          �����������͵
/1Y �3       18� 6A          � 0 � 0 � 1 �
 2A �4       17� /6Y         � 0 � 1 � 1 �
 2B �5   74  16� 5B          � 1 � 0 � 1 �
/2Y �6  804  15� 5A          � 1 � 1 � 0 �
 3A �7       14� /5Y         �������������
 3B �8       13� 4B
/3Y �9       12� 4A
GND �10      11� /4Y
    ������������
#
74805
Hex 2-input NOR gates/line drivers.

    ����������Ŀ             �����������Ŀ           ___
 1A �1  ���� 20� VCC         � A � B �/Y �      /Y = A+B
 1B �2       19� 6B          �����������͵
/1Y �3       18� 6A          � 0 � 0 � 1 �
 2A �4       17� /6Y         � 0 � 1 � 0 �
 2B �5   74  16� 5B          � 1 � 0 � 0 �
/2Y �6  805  15� 5A          � 1 � 1 � 0 �
 3A �7       14� /5Y         �������������
 3B �8       13� 4B
/3Y �9       12� 4A
GND �10      11� /4Y
    ������������
#
74808
Hex 2-input AND gates/line drivers.

    ����������Ŀ             �����������Ŀ
 1A �1  ���� 20� VCC         � A � B � Y �       Y = AB
 1B �2       19� 6B          �����������͵
 1Y �3       18� 6A          � 0 � 0 � 0 �
 2A �4       17� 6Y          � 0 � 1 � 0 �
 2B �5   74  16� 5B          � 1 � 0 � 0 �
 2Y �6  808  15� 5A          � 1 � 1 � 1 �
 3A �7       14� 5Y          �������������
 3B �8       13� 4B
 3Y �9       12� 4A
GND �10      11� 4Y
    ������������
#
74821
10-bit 3-state D flip-flop/bus driver.

    ����������Ŀ             ���������������Ŀ
/OE �1  ���� 24� VCC         �/OE�CLK� D � Q �
 D1 �2       23� Q1          ���������������͵
 D2 �3       22� Q2          � 1 � X � X � Z �
 D3 �4       21� Q3          � 0 � / � 0 � 0 �
 D4 �5       20� Q4          � 0 � / � 1 � 1 �
 D5 �6   74  19� Q5          � 0 �!/ � X � - �
 D6 �7  821  18� Q6          �����������������
 D7 �8       17� Q7
 D8 �9       16� Q8
 D9 �10      15� Q9
D10 �11      14� Q10
GND �12      13� CLK
    ������������
#
74822
10-bit 3-state inverting D flip-flop/bus driver.

    ����������Ŀ             ���������������Ŀ
/OE �1  ���� 24� VCC         �/OE�CLK� D �/Q �
 D1 �2       23� /Q1         ���������������͵
 D2 �3       22� /Q2         � 1 � X � X � Z �
 D3 �4       21� /Q3         � 0 � / � 0 � 1 �
 D4 �5       20� /Q4         � 0 � / � 1 � 0 �
 D5 �6   74  19� /Q5         � 0 �!/ � X � - �
 D6 �7  822  18� /Q6         �����������������
 D7 �8       17� /Q7
 D8 �9       16� /Q8
 D9 �10      15� /Q9
D10 �11      14� /Q10
GND �12      13� CLK
    ������������
#
74823
9-bit 3-state D flip-flop/bus driver with clock enable and reset.

     ����������Ŀ
 /OE �1  ���� 24� VCC
  D1 �2       23� Q1
  D2 �3       22� Q2
  D3 �4       21� Q3
  D4 �5       20� Q4
  D5 �6   74  19� Q5
  D6 �7  823  18� Q6
  D7 �8       17� Q7
  D8 �9       16� Q8
  D9 �10      15� Q9
/RST �11      14� /CLKEN
 GND �12      13� CLK
     ������������
#
74825
8-bit 3-state D flip-flop/bus driver with three output enables, clock enable
and reset.

     ����������Ŀ
/OE1 �1  ���� 24� VCC
/OE2 �2       23� /OE3
  D1 �3       22� Q1
  D2 �4       21� Q2
  D3 �5       20� Q3
  D4 �6   74  19� Q4
  D5 �7  825  18� Q5
  D6 �8       17� Q6
  D7 �9       16� Q7
  D8 �10      15� Q8
/RST �11      14� /CLKEN
 GND �12      13� CLK
     ������������
#
74827
10-bit 3-state noninverting buffer/line driver.

     ����������Ŀ
/OE1 �1  ���� 24� VCC
  A1 �2       23� Y1
  A2 �3       22� Y2
  A3 �4       21� Y3
  A4 �5       20� Y4
  A5 �6  742  19� Y5
  A6 �7  827  18� Y6
  A7 �8       17� Y7
  A8 �9       16� Y8
  A9 �10      15� Y9
 A10 �11      14� Y10
 GND �12      13� /OE2
     ������������
#
7483
4-bit binary full adder with fast carry.

    ����������Ŀ
 A4 �1  ���� 16� B4          �=A+B+CIN
 �3 �2       15� �4
 A3 �3       14� COUT
 B3 �4       13� CIN
VCC �5  7483 12� GND
 �2 �6       11� B1
 B2 �7       10� A1
 A2 �8        9� �1
    ������������
#
74832
Hex 2-input OR gates/line drivers.

    ����������Ŀ             �����������Ŀ
 1A �1  ���� 20� VCC         � A � B � Y �       Y = A+B
 1B �2       19� 6B          �����������͵
 1Y �3       18� 6A          � 0 � 0 � 0 �
 2A �4       17� 6Y          � 0 � 1 � 1 �
 2B �5   74  16� 5B          � 1 � 0 � 1 �
 2Y �6  832  15� 5A          � 1 � 1 � 1 �
 3A �7       14� 5Y          �������������
 3B �8       13� 4B
 3Y �9       12� 4A
GND �10      11� 4Y
    ������������
#
74833
8-bit 3-state noninverting bus transceiver with parity generator/checker
and parity register.

       ����������Ŀ
  /OEA �1  ���� 24� VCC
    A1 �2       23� B1
    A2 �3       22� B2
    A3 �4       21� B3
    A4 �5       20� B4
    A5 �6   74  19� B5
    A6 �7  833  18� B6
    A7 �8       17� B7
    A8 �9       16� B8
/ERROR �10      15� PAR
  /CLR �11      14� /OEB
   GND �12      13� CLK
       ������������
#
74841
10-bit 3-state transparent latch/bus driver.

    ����������Ŀ             ���������������Ŀ
/OE �1  ���� 24� VCC         �/OE� LE� D � Q �
 D1 �2       23� Q1          ���������������͵
 D2 �3       22� Q2          � 1 � X � X � Z �
 D3 �4       21� Q3          � 0 � 0 � X � - �
 D4 �5       20� Q4          � 0 � 1 � 0 � 0 �
 D5 �6   74  19� Q5          � 0 � 1 � 1 � 1 �
 D6 �7  841  18� Q6          �����������������
 D7 �8       17� Q7
 D8 �9       16� Q8
 D9 �10      15� Q9
D10 �11      14� Q10
GND �12      13� LE
    ������������
#
74843
9-bit 3-state transparent latch/bus driver with set and reset.

     ����������Ŀ            �������������������������Ŀ
 /OE �1  ���� 24� VCC        �/RST�/SET�/OE� LE� D � Q �
  D1 �2       23� Q1         �������������������������͵
  D2 �3       22� Q2         �  0 �  1 � 0 � X � X � 0 �
  D3 �4       21� Q3         �  1 �  0 � 0 � X � X � 0 �
  D4 �5       20� Q4         �  X �  X � 1 � X � X � Z �
  D5 �6   74  19� Q5         �  1 �  1 � 0 � 0 � X � - �
  D6 �7  843  18� Q6         �  1 �  1 � 0 � 1 � 0 � 0 �
  D7 �8       17� Q7         �  1 �  1 � 0 � 1 � 1 � 1 �
  D8 �9       16� Q8         ���������������������������
  D9 �10      15� Q9
/RST �11      14� /SET
 GND �12      13� LE
     ������������
#
74845
8-bit 3-state transparent latch/bus driver with three output enables,
set and reset.

     ����������Ŀ
/OE1 �1  ���� 24� VCC
/OE2 �2       23� /OE3
  D1 �3       22� Q1
  D2 �4       21� Q2
  D3 �5       20� Q3
  D4 �6   74  19� Q4
  D5 �7  845  18� Q5
  D6 �8       17� Q6
  D7 �9       16� Q7
  D8 �10      15� Q8
/RST �11      14� /SET
 GND �12      13� LE
     ������������
#
7485
4-bit noninverting magnitude comparator with cascade inputs.

     ����������Ŀ
  B3 �1  ���� 16� VCC
IAB �4       13� A2
OA>B �5  7485 12� A1
OA=B �6       11� B1
OAB �3       22� A7
  B7 �4       21� A6
  B6 �5       20� A5
  B5 �6   74  19� A4
  B4 �7  885  18� A3
  B3 �8       17� A2
  B2 �9       16� A1
  B1 �10      15� A0
  B0 �11      14� OAB
     ������������
#
74899
8-bit 3-state noninverting latchable bus transceiver with parity
generator/checker and independent latch-enable inputs.

      ����������Ŀ
 O//E �1  ���� 28� VCC
/ERRA �2       27� /OEAB
 LEAB �3       26� B1
   A1 �4       25� B2
   A2 �5       24� B3
   A3 �6       23� B4
   A4 �7   74  22� B5
   A5 �8  899  21� B6
   A6 �9       20� B7
   A7 �10      19� B8
   A8 �11      18� BPAR
 APAR �12      17� LEBA
/OEBA �13      16� /SEL
  GND �14      15� /ERRB
      ������������
#
7490
4-bit asynchronous decade counter with /2 and /5 sections, set(9) and reset.

      ����������Ŀ
/CLK1 �1  ���� 14� /CLK0
 RST1 �2       13�
 RST2 �3       12� Q0
      �4  7490 11� Q3
  VCC �5       10� GND
 SET1 �6        9� Q1
 SET2 �7        8� Q2
      ������������
#
7491
8-bit serial-in serial-out shift register with gated serial inputs and
complementary outputs.

    ����������Ŀ
    �1  ���� 14� /QH
    �2       13� QH
    �3       12� A
    �4  7491 11� B
VCC �5       10� GND
    �6        9� CLK
    �7        8�
    ������������
#
7492
4-bit asynchronous divide-by-twelve counter with /2 and /6 sections and reset.

      ����������Ŀ
/CLK1 �1  ���� 14� /CLK0
      �2       13�
      �3       12� Q0
      �4  7492 11� Q3
  VCC �5       10� GND
 RST1 �6        9� Q1
 RST2 �7        8� Q2
      ������������
#
7493
4-bit asynchronous binary counter with /2 and /8 sections and reset.

      ����������Ŀ
/CLK1 �1  ���� 14� /CLK0
 RST1 �2       13�
 RST2 �3       12� Q0
      �4  7493 11� Q3
  VCC �5       10� GND
      �6        9� Q1
      �7        8� Q2
      ������������
#
7495
4-bit shift register with separate shift and parallel-load clocks.

      ����������Ŀ
   SA �1  ���� 14� VCC
    A �2       13� QA
    B �3       12� QB
    C �4  7495 11� QC
    D �5       10� QD
L//SH �6        9� SHCLK
  GND �7        8� LDCLK
      ������������
#
74956
8-bit 3-state noninverting latched transceiver.

     ����������Ŀ
LEAB �1  ���� 24� VCC
 SAB �2       23� LEBA
 DIR �3       22� SBA
  A1 �4       21� /OE
  A2 �5       20� B1
  A3 �6   74  19� B2
  A4 �7  956  18� B3
  A5 �8       17� B4
  A6 �9       16� B5
  A7 �10      15� B6
  A8 �11      14� B7
 GND �12      13� B8
     ������������
#
7496
5-bit shift register with asynchronous reset and load.

    ����������Ŀ
CLK �1  ���� 16� /RST
  A �2       15� QA
  B �3       14� QB
  C �4       13� QC
VCC �5  7496 12� GND
  D �6       11� QD
  E �7       10� QE
 PE �8        9� SA
    ������������
#
7497
6-bit synchronous binary rate multiplier.
Can perform fixed-rate or variable-rate frequency division.
Output frequency is equal to input frequency multiplied by the rate input M
and divided by 64.

      ����������Ŀ
   B1 �1  ���� 16� VCC
   B4 �2       15� B3
   B5 �3       14� B2
   B0 �4       13� RST
    Z �5  7497 12� U/CAS
    Y �6       11� ENin
ENout �7       10� STRB
  GND �8        9� CLK
      ������������
#
74990
8-bit transparent latch with readback.

      ����������Ŀ
/OERB �1  ���� 20� VCC
   D1 �2       19� Q1
   D2 �3       18� Q2
   D3 �4       17� Q3
   D4 �5   74  16� Q4
   D5 �6  990  15� Q5
   D6 �7       14� Q6
   D7 �8       13� Q7
   D8 �9       12� Q8
  GND �10      11� LE
      ������������
#
74992
9-bit 3-state transparent latch with readback and reset.

      ����������Ŀ
/OERB �1  ���� 24� VCC
   D1 �2       23� Q1
   D2 �3       22� Q2
   D3 �4       21� Q3
   D4 �5       20� Q4
   D5 �6   74  19� Q5
   D6 �7  992  18� Q6
   D7 �8       17� Q7
   D8 �9       16� Q8
   D9 �10      15� Q9
 /RST �11      14� /OE
  GND �12      13� LE
      ������������
#
74994
10-bit transparent latch with readback.

      ����������Ŀ
/OERB �1  ���� 24� VCC
   D1 �2       23� Q1
   D2 �3       22� Q2
   D3 �4       21� Q3
   D4 �5       20� Q4
   D5 �6   74  19� Q5
   D6 �7  994  18� Q6
   D7 �8       17� Q7
   D8 �9       16� Q8
   D9 �10      15� Q9
  D10 �11      14� Q10
  GND �12      13� LE
      ������������
#
75173, LTC488
Quad RS485 line receiver.
Note the unusual ORed output enables.

    ����������Ŀ             �������������������Ŀ
 B1 �1  ���� 16� VCC         �  A-B  � OE�/OE� Y �
 A1 �2       15� B4          �������������������͵
 Y1 �3       14� A4          �>+200mV� 1 � X � 1 �
 OE �4       13� Y4          �>+200mV� X � 0 � 1 �
 Y2 �5 75173 12� /OE         �<-200mV� 1 � X � 0 �
 A2 �6       11� Y3          �<-200mV� X � 0 � 0 �
 B2 �7       10� A3          �   X   � 0 � 1 � Z �
GND �8        9� B3          ���������������������
    ������������
#
75174, LTC485
Quad RS485 line driver.

     ����������Ŀ            ���������������Ŀ
 1A1 �1  ���� 16� VCC        � A � EN� Y �/Y �
 1Y1 �2       15� 2A2        ���������������͵
/1Y1 �3       14� 2Y2        � 0 � 1 � 0 � 1 �
 1EN �4       13� /2Y2       � 1 � 1 � 1 � 0 �
/1Y2 �5 75174 12� 2EN        � X � 0 � Z � Z �
 1Y2 �6       11� /2Y1       �����������������
 1A2 �7       10� 2Y1
 GND �8        9� 2A1
     ������������
#
75175, LTC489
Quad RS485 line receiver.

    ����������Ŀ             ���������������Ŀ
1B1 �1  ���� 16� VCC         �  A-B  � OE� Y �
1A1 �2       15� 2B2         ���������������͵
1Y1 �3       14� 2A2         �>+200mV� 1 � 1 �
1OE �4       13� 2Y2         �<-200mV� 1 � 0 �
1Y2 �5 75175 12� 2OE         �   X   � 0 � Z �
1A2 �6       11� 2Y1         �����������������
1B2 �7       10� 2A1
GND �8        9� 2B1
    ������������
#
75176, LTC485
RS485 line transceiver.
                             Receiver:           Transmitter:
    ����������Ŀ             ���������������Ŀ   ���������������Ŀ
  Y �1  ����  8� VCC         �  A-B  �/OE� Y �   � D �DEN� A � B �
/OE �2        7� B           ���������������͵   ���������������͵
DEN �3  75176 6� A           �>+200mV� 0 � 1 �   � 0 � 1 � 0 � 1 �
  D �4        5� GND         �<-200mV� 0 � 0 �   � 1 � 1 � 1 � 0 �
    ������������             �   X   � 1 � Z �   � X � 0 � Z � Z �
                             �����������������   �����������������
#
765
Floppy disk controller.

       ��������������Ŀ
   RST �1    ����   40� VCC
   /RD �2           39� /RW SEEK
   /WR �3           38� LCT DIR
   /CE �4           37� FR  STEP
D/S A0 �5           36� HDL
    D0 �6           35� RDY
    D1 �7           34� WP  TS
    D2 �8           33� FLT TR00
    D3 �9           32� PS0
    D4 �10   765    31� PS1
    D5 �11   FDC    30� WDA
    D6 �12          29� US0
    D7 �13          28� US1
   DRQ �14          27� HD
 /DACK �15          26� MFM
    TC �16          25� WE
   IDX �17          24� VCO SYNC
   INT �18          23� RDD
   CLK �19          22� RDW
   GND �20          21� WCLK
       ����������������
#
78Hxx, 78H05, 78H12, 78H15, 78H24
Fixed voltage 5A positive power supply regulator
Vin must exceed Vout by at least 3V, but may not exceed 40V.

TO 220
���Ŀ2
���͵
� ��
�����    1: Vin
 ���     2: GND
 ���     3: Vout
1 2 3
#
78Lxx, 78L05, 78L06, 78L07, 78L08, 78L09, 78L10, 78L12, 78L15, 78L24
Fixed voltage 100mA positive power supply regulator.
Vin must exceed Vout by at least 3V, but may not exceed 40V.

TO 92
���ķ
� ��
���½    1: Vin
 ���     2: GND
 ���     3: Vout
1 2 3
#
78Txx, 78T05, 78T12, 78T15, 78T24
Fixed voltage 3A positive power supply regulator
Vin must exceed Vout by at least 3V, but may not exceed 40V.

TO 220
���Ŀ2
���͵
� ��
�����    1: Vin
 ���     2: GND
 ���     3: Vout
1 2 3
#
78xx, 7805, 7806, 7807, 7808, 7809, 7810, 7812, 7815, 7824
Fixed voltage 1A positive power supply regulator.
Vin must exceed Vout by at least 3V, but may not exceed 40V.

TO 220
���Ŀ2
���͵
� ��
�����    1: Vin
 ���     2: GND
 ���     3: Vout
1 2 3
#
79Lxx, 79L05, 79L06, 79L07, 79L08, 79L09, 79L10, 79L12, 79L15, 79L24
Fixed voltage 100mA negative power supply regulator.
Vin must exceed Vout by at least 3V, but may not exceed -40V.

TO 92
���ķ
� ��
���½    1: GND
 ���     2: Vin
 ���     3: Vout
1 2 3
#
79xx, 7905, 7906, 7907, 7908, 7909, 7910, 7912, 7915, 7924
Fixed voltage 1A negative power supply regulator
Vin must exceed Vout by at least 3V, but may not exceed -40V.

TO 220
���Ŀ2
���͵
� ��
�����    1: GND
 ���     2: Vin
 ���     3: Vout
1 2 3
#
8048, 8049, 8050, 8748, 8749, 8035, 8039, 8040 (DIP)
Intel 8048-series microcontroller.

      ��������������Ŀ
   T0 �1    ����   40� VCC
   X1 �2           39� T1
   X0 �3           38� P2.7
 /RST �4           37� P2.6
  /SS �5           36� P2.5
 /INT �6           35� P2.4
   EA �7           34� P1.7
  /RD �8           33� P1.6
/PSEN �9           32� P1.5
  /WR �10   8048   31� P1.4
  ALE �11  series  30� P1.3
  DB0 �12          29� P1.2
  DB1 �13          28� P1.1
  DB2 �14          27� P1.0
  DB3 �15          26� VCC_RAM VPP
  DB4 �16          25� PROG
  DB5 �17          24� P2.3
  DB6 �18          23� P2.2
  DB7 �19          22� P2.1
  GND �20          21� P2.0
      ����������������
#
8048, 8049, 8050, 8748, 8749, 8035, 8039, 8040 (PLCC)
Intel 8048-series microcontroller.

PLCC44
���������������������������������������������������������������Ŀ
�  7 /INT       � 18 DB4        � 29 VCCRAM VPP � 40 P2.5       �
�  8 EA         � 19 DB5        � 30 P1.0       � 41 P2.6       �
�  9 /RD        � 20 DB6        � 31 P1.1       � 42 P2.7       �
� 10 /PSEN      � 21 DB7        � 32 P1.2       � 43 T1         �
� 11 /WR        � 22 GND        � 33 P1.3       � 44 VCC        �
� 12            � 23            � 34            �  1            �
� 13 ALE        � 24 P2.0       � 35 P1.4       �  2 T0         �
� 14 DB0        � 25 P2.1       � 36 P1.5       �  3 X1         �
� 15 DB1        � 26 P2.2       � 37 P1.6       �  4 X0         �
� 16 DB2        � 27 P2.3       � 38 P1.7       �  5 /RST       �
� 17 DB3        � 28 PROG       � 39 P2.4       �  6 /SS        �
�����������������������������������������������������������������
#
8051, 8052, 8054, 8058, 8751, 8752, 8754, 8758, 8031, 8032 (DIP)
Intel 8051-series microcontroller.

           ��������������Ŀ
   T2 P1.0 �1    ����   40� VCC
 T2EX P1.1 �2           39� P0.0 AD0
  ECI P1.2 �3           38� P0.1 AD1
 CEX0 P1.3 �4           37� P0.2 AD2
 CEX1 P1.4 �5           36� P0.3 AD3
 CEX2 P1.5 �6           35� P0.4 AD4
 CEX3 P1.6 �7           34� P0.5 AD5
 CEX4 P1.7 �8           33� P0.6 AD6
       RST �9           32� P0.7 AD7
  RxD P3.0 �10   8051   31� /EA VPP
  TxD P3.1 �11  series  30� ALE /PROG
/INT0 P3.2 �12          29� /PSEN
/INT1 P3.3 �13          28� P2.7 A15
   T0 P3.4 �14          27� P2.6 A14
   T1 P3.5 �15          26� P2.5 A13
  /WR P3.6 �16          25� P2.4 A12
  /RD P3.7 �17          24� P2.3 A11
        X0 �18          23� P2.2 A10
        X1 �19          22� P2.1 A9
       GND �20          21� P2.0 A8
           ����������������
#
8051, 8052, 8054, 8058, 8751, 8752, 8754, 8758, 8031, 8032 (PLCC)
Intel 8051-series microcontroller.
The 8x54 and 8x58 have an extra GND pin.

PLCC44
���������������������������������������������������������������Ŀ
�  7 P1.5 CEX2  � 18 P3.6 /WR   � 29 P2.5 A13   � 40 P0.3 AD3   �
�  8 P1.6 CEX3  � 19 P3.7 /RD   � 30 P2.6 A14   � 41 P0.2 AD2   �
�  9 P1.7 CEX4  � 20 X0         � 31 P2.7 A15   � 42 P0.1 AD1   �
� 10 RST        � 21 X1         � 32 /PSEN      � 43 P0.0 AD0   �
� 11 P3.0 RxD   � 22 GND        � 33 ALE /PROG  � 44 VCC        �
� 12            � 23            � 34            �  1 (GND)      �
� 13 P3.1 TxD   � 24 P2.0 A8    � 35 /EA VPP    �  2 P1.0 T2    �
� 14 P3.2 /INT0 � 25 P2.1 A9    � 36 P0.7 AD7   �  3 P1.1 T2EX  �
� 15 P3.3 /INT1 � 26 P2.2 A10   � 37 P0.6 AD6   �  4 P1.2 ECI   �
� 16 P3.4 T0    � 27 P2.3 A11   � 38 P0.5 AD5   �  5 P1.3 CEX0  �
� 17 P3.5 T1    � 28 P2.4 A12   � 39 P0.4 AD4   �  6 P1.4 CEX1  �
�����������������������������������������������������������������
#
8085
Intel 8085 CPU.

       ��������������Ŀ
    X1 �1    ����   40� VCC
    X2 �2           39� HOLD
RSTOUT �3           38� HLDA
   SOD �4           37� CLK
   SID �5           36� /RSTIN
  TRAP �6           35� RDY
 RST75 �7           34� IO//M
 RST65 �8           33� S1
 RST55 �9           32� /RD
  INTR �10   8085   31� /WR
 /INTA �11          30� ALE
   AD0 �12          29� S0
   AD1 �13          28� A15
   AD2 �14          27� A14
   AD3 �15          26� A13
   AD4 �16          25� A12
   AD5 �17          24� A11
   AD6 �18          23� A10
   AD7 �19          22� A9
   GND �20          21� A8
       ����������������
#
8086
Intel 8086 CPU.

     ��������������Ŀ
 GND �1    ����   40� VCC
AD14 �2           39� AD15
AD13 �3           38� A16  S3
AD12 �4           37� A17  S4
AD11 �5           36� A18  S5
AD10 �6           35� A19  S6
 AD9 �7           34� /BHE S7
 AD8 �8           33� MN//MX
 AD7 �9           32� /RD
 AD6 �10          31� /RQ//GT0 HOLD
 AD5 �11   8086   30� /RQ//GT1 HLDA
 AD4 �12          29� /LOCK    /WR
 AD3 �13          28� /S2      M//IO
 AD2 �14          27� /S1      DT//R
 AD1 �15          26� /S0      /DEN
 AD0 �16          25� QS0      ALE
 NMI �17          24� QS1      /INTA
INTR �18          23� /TEST
 CLK �19          22� READY
 GND �20          21� RST
     ����������������
#
8243
8048 Port expander.

     ��������������Ŀ
P5.0 �1    ����   24� VCC
P4.0 �2           23� P5.1
P4.1 �3           22� P5.2
P4.2 �4           21� P5.3
P4.3 �5           20� P6.0
 /CS �6           19� P6.1
PROG �7    8243   18� P6.2
P2.3 �8           17� P6.3
P2.2 �9           16� P7.3
P2.1 �10          15� P7.2
P2.0 �11          14� P7.1
 GND �12          13� P7.0
     ����������������
#
8250, 16450
Asynchronous serial interface controller.

        ��������������Ŀ
     D0 �1    ����   40� VCC
     D1 �2           39� /RI
     D2 �3           38� /DCD
     D3 �4           37� /DSR
     D4 �5           36� /CTS
     D5 �6           35� MR
     D6 �7           34� /OUT1
     D7 �8           33� /DTR
   RCLK �9           32� /RTS
    SIN �10  16450   31� /OUT2
   SOUT �11   8250   30� INTR
    CS0 �12          29� CSOUT
    CS1 �13          28� A0
   /CS2 �14          27� A1
/CLKOUT �15          26� A2
     X1 �16          25� /ADS
     X0 �17          24�
    /WR �18          23� DDIS
     WR �19          22� RD
    GND �20          21� /RD
        ����������������
#
8253, 8254
Programmable interval timer/counter.

     ��������������Ŀ
  D7 �1    ����   24� VCC
  D6 �2           23� /WR
  D5 �3           22� /RD
  D4 �4           21� /CE
  D3 �5           20� A1
  D2 �6    8253   19� A0
  D1 �7    8254   18� CLK2
  D0 �8           17� OUT2
CLK0 �9           16� G2
OUT0 �10          15� CLK1
  G0 �11          14� G1
 GND �12          13� OUT1
     ����������������
#
8255
Parallel Peripheral Interface.

    ��������������Ŀ
PA3 �1    ����   40� PA4
PA2 �2           39� PA5
PA1 �3           38� PA6
PA0 �4           37� PA7
/RD �5           36� /WR
/CE �6           35� RST
GND �7           34� D0
 A1 �8           33� D1
 A0 �9           32� D2
PC7 �10   8255   31� D3
PC6 �11          30� D4
PC5 �12          29� D5
PC4 �13          28� D6
PC0 �14          27� D7
PC1 �15          26� VCC
PC2 �16          25� PB7
PC3 �17          24� PB6
PB0 �18          23� PB5
PB1 �19          22� PB4
PB2 �20          21� PB3
    ����������������
#
8400, Z8400, Z80CPU
Zilog Z80 CPU.

      ��������������Ŀ
  A11 �1    ����   40� A10
  A12 �2           39� A9
  A13 �3           38� A8
  A14 �4           37� A7
  A15 �5           36� A6
  CLK �6           35� A5
   D4 �7           34� A4
   D3 �8           33� A3
   D5 �9           32� A2
   D6 �10   Z8400  31� A1
  VCC �11    CPU   30� A0
   D2 �12          29� GND
   D7 �13          28� /RFSH
   D0 �14          27� /M1
   D1 �15          26� /RST
 /INT �16          25� /BUSRQ
 /NMI �17          24� /WAIT
/HALT �18          23� /BUSAK
/MREQ �19          22� /WR
/IORQ �20          21� /RD
      ����������������
#
8410, Z8410, Z80DMA
Z80 DMA controller.

          ��������������Ŀ
       A5 �1    ����   40� A6
       A4 �2           39� A7
       A3 �3           38� IEI
       A2 �4           37� /INT /PULSE
       A1 �5           36� IEO
       A0 �6           35� D0
      CLK �7           34� D1
      /WR �8           33� D2
      /RD �9           32� D3
    /IORQ �10   Z8410  31� D4
      VCC �11    DMA   30� GND
    /MREQ �12          29� D5
     /BAO �13          28� D6
     /BAI �14          27� D7
   /BUSRQ �15          26� /M1
/CE /WAIT �16          25� RDY
      A15 �17          24� A8
      A14 �18          23� A9
      A13 �19          22� A10
      A12 �20          21� A11
          ����������������
#
8420, Z8420, Z80PIO
Z80 parallel I/O.

       ��������������Ŀ
    D2 �1    ����   40� D3
    D7 �2           39� D4
    D6 �3           38� D5
   /CE �4           37� /M1
C/D A1 �5           36� /IORQ
B/A A0 �6           35� /RD
   PA7 �7           34� PB7
   PA6 �8           33� PB6
   PA5 �9           32� PB5
   PA4 �10   Z8420  31� PB4
   GND �11    PIO   30� PB3
   PA3 �12          29� PB2
   PA2 �13          28� PB1
   PA1 �14          27� PB0
   PA0 �15          26� VCC
 /ASTB �16          25� CLK
 /BSTB �17          24� IEI
  ARDY �18          23� /INT
    D0 �19          22� IEO
    D1 �20          21� BRDY
       ����������������
#
8430, Z8430
Z80 Counter-Timer Circuit.

        ��������������Ŀ
     D4 �1    ����   28� D3
     D5 �2           27� D2
     D6 �3           26� D1
     D7 �4           25� D0
    GND �5           24� VCC
    /RD �6           23� CLK0 TRG0
ZC0 TO0 �7   Z8430   22� CLK1 TRG1
ZC1 TO1 �8    CTC    21� CLK2 TRG2
ZC2 TO2 �9           20� CLK3 TRG3
  /IORQ �10          19� A1
    IEO �11          18� A0
   /INT �12          17� /RST
    IEI �13          16� /CE
    /M1 �14          15� CLK
        ����������������
#
8440, 8470, Z8440, Z80SIO0, Z8470, Z80DART
Z80 dual async/sync serial I/O.
Z8470 has no synchronous capabilities.

        ��������������Ŀ
     D1 �1    ����   40� D0
     D3 �2           39� D2
     D5 �3           38� D4
     D7 �4           37� D6
   /INT �5           36� /IORQ
    IEI �6           35� /CE
    IEO �7           34� A0 B/A
    /M1 �8           33� A1 C/D
    VCC �9           32� /RD
/W_RDYA �10   Z8440  31� GND
 /SYNCA �11   SIO-0  30� /W_RDYB
   RxDA �12          29� /SYNCB
  /RxCA �13          28� RxDB
  /TxCA �14          27� /RxTxCB
   TxDA �15          26� TxDB
  /DTRA �16          25� /DTRB
  /RTSA �17          24� /RTSB
  /CTSA �18          23� /CTSB
  /DCDA �19          22� /DCDB
    CLK �20          21� /RST
        ����������������
#
8441, Z8441, Z80SIO1
Z80 dual async/sync serial I/O (bonding option #1).

        ��������������Ŀ
     D1 �1    ����   40� D0
     D3 �2           39� D2
     D5 �3           38� D4
     D7 �4           37� D6
   /INT �5           36� /IORQ
    IEI �6           35� /CE
    IEO �7           34� A0 B/A
    /M1 �8           33� A1 C/D
    VCC �9           32� /RD
/W_RDYA �10   Z8441  31� GND
 /SYNCA �11   SIO-1  30� /W_RDYB
   RxDA �12          29� /SYNCB
  /RxCA �13          28� RxDB
  /TxCA �14          27� /RxCB
   TxDA �15          26� /TxCB
  /DTRA �16          25� TxDB
  /RTSA �17          24� /RTSB
  /CTSA �18          23� /CTSB
  /DCDA �19          22� /DCDB
    CLK �20          21� /RST
        ����������������
#
8442, Z8442, Z80SIO2
Z80 dual async/sync serial I/O (bonding option #2).

         ��������������Ŀ
      D1 �1    ����   40� D0
      D3 �2           39� D2
      D5 �3           38� D4
      D7 �4           37� D6
    /INT �5           36� /IORQ
     IEI �6           35� /CE
     IEO �7           34� A0 B/A
     /M1 �8           33� A1 C/D
     VCC �9           32� /RD
 /W_RDYA �10   Z8442  31� GND
  /SYNCA �11   SIO-2  30� /W_RDYB
    RxDA �12          29� RxDB
   /RxCA �13          28� /RxCB
   /TxCA �14          27� /TxCB
    TxDA �15          26� TxDB
   /DTRA �16          25� /DTRB
   /RTSA �17          24� /RTSB
   /CTSA �18          23� /CTSB
   /DCDA �19          22� /DCDB
     CLK �20          21� /RST
         ����������������
#
8530, 8531, Z8530, Z8531
Zilog Serial Comminucations Controller.
Z8531 has no synchronous capabilities.

          ��������������Ŀ
       D1 �1    ����   40� D0
       D3 �2           39� D2
       D5 �3           38� D4
       D7 �4           37� D6
     /INT �5           36� /RD
      IEO �6           35� /WR
      IEI �7           34� A0 A/B
   /INTAK �8           33� /CE
      VCC �9           32� A1 D/C
  /W_REQA �10   Z8530  31� GND
   /SYNCA �11    SCC   30� /W_REQB
   /RTxCA �12          29� /SYNCB
     RxDA �13          28� /RTxCB
   /TRxCA �14          27� RxDB
     TxDA �15          26� /TRxCB
/DTR_REQA �16          25� TxDB
    /RTSA �17          24� /DTR_REQB
    /CTSA �18          23� /RTSB
    /DCDA �19          22� /CTSB
      CLK �20          21� /DCDB
          ����������������
#
8570
I�C 256x8 static RAM.
Address is 1010xxx where x can be specified by the A0-2 inputs.

    ����������Ŀ
 A0 �1  ����  8� VCC
 A1 �2        7� GND
 A2 �3  8570  6� SCL
GND �4        5� SDA
    ������������
#
8571
I�C 128x8 static RAM.
Address is 1010xxx where x can be specified by the A0-2 inputs.

    ����������Ŀ
 A0 �1  ����  8� VCC
 A1 �2        7� GND
 A2 �3  8571  6� SCL
GND �4        5� SDA
    ������������
#
8581, 8572
I�C 128x8 EEPROM.
Address is 1010xxx where x can be specified by the A0-2 inputs.

    ����������Ŀ
 A0 �1  ����  8� VCC
 A1 �2  8572  7� GND
 A2 �3  8581  6� SCL
GND �4        5� SDA
    ������������
#
8582
I�C 256x8 EEPROM.
Address is 1010xxx where x can be specified by the A0-2 inputs.

    ����������Ŀ
 A0 �1  ����  8� VCC
 A1 �2        7� GND
 A2 �3  8582  6� SCL
GND �4        5� SDA
    ������������
#
8583
I�C Clock/Calendar with 240x8 static RAM.
Address is 101000x where x can be specified by the A0 input.

    ����������Ŀ
 X1 �1  ����  8� VCC
 X0 �2        7� /INT
 A0 �3  8583  6� SCL
GND �4        5� SDA
    ������������
#
8592
I�C 2x256x8 EEPROM.
Address is 1010xxy where x can be specified by the A1-2 inputs,
and y selects the 256-byte bank to use.
A0 has no function, but must be connected to GND or VCC.

    ����������Ŀ
 A0 �1  ����  8� VCC
 A1 �2        7� GND
 A2 �3  8582  6� SCL
GND �4        5� SDA
    ������������
#
9306
Serial 16x16 EEPROM.

    ����������Ŀ
 CD �1  ����  8� VCC
CLK �2        7�
 DI �3  9306  6�
 DO �4        5� GND
    ������������
#
9346
Serial 64x16 EEPROM.

    ����������Ŀ
 CD �1  ����  8� VCC
CLK �2        7�
 DI �3  9346  6�
 DO �4        5� GND
    ������������
#
9356
Serial 256x8/128x16 EEPROM.

    ����������Ŀ
 CD �1  ����  8� VCC
CLK �2        7�
 DI �3  9356  6� x16//x8
 DO �4        5� GND
    ������������
#
9366
Serial 512x8/256x16 EEPROM.

    ����������Ŀ
 CD �1  ����  8� VCC
CLK �2        7�
 DI �3  9366  6� x16//x8
 DO �4        5� GND
    ������������
#
CNY74-2
Dual optocouplers.

   ����������Ŀ
1A �1  ����  8� 1E
1K �2  CNY   7� 1C
2K �3  74-2  6� 2C
2A �4        5� 2E
   ������������
#
CNY74-4
Quad optocouplers.

   ����������Ŀ
1A �1  ���� 16� 1E
1K �2       15� 1C
2K �3       14� 2C
2A �4  CNY  13� 2E
3A �5  74-4 12� 3E
3K �6       11� 3C
4K �7       10� 4C
4A �8        9� 4E
   ������������
#
DS1202
Real-time clock with 3-wire serial interface and 24 bytes RAM.

    ����������Ŀ
    �1  ����  8� VCC
 X1 �2   DS   7� CLK
 X2 �3  1202  6� DQ
GND �4        5� /RST
    ������������
#
DS1210
Nonvolatile SRAM controller chip.
TOL selects power-fail VCC level, based on 5% tolerance when 0 or
10% tolerance when 1.

      ����������Ŀ           ������������Ŀ
 VCCo �1  ����  8� VCC       �/EN�VCC �/Y �
VBAT1 �2   DS   7� VBAT2     ������������͵
  TOL �3  1210  6� /Y        � 1 � OK � 1 �
  GND �4        5� /EN       � 0 � OK � 0 �
      ������������           � X � LO � 1 �
                             ��������������
#
DS1211
1-of-8 inverting decoder/nonvolatile SRAM controller chip.
TOL selects power-fail VCC level, based on 5% tolerance when 0 or
10% tolerance when 1.
The Dallas data book suggests this is actually a repackaged DS1212.

      ����������Ŀ           ����������������������������������������Ŀ
VBAT1 �1  ���� 20� VCC       �/EN� S2� S1� S0�VCC �/Y0�/Y1�...�/Y7�/PF�
 VCCo �2       19� VBAT2     ����������������������������������������͵
  TOL �3       18� /EN       � X � X � X � X � LO � 1 � 1 � 1 � 1 � 0 �
  /PF �4       17� /Y0       � 1 � 0 � 0 � 0 � OK � 0 � 1 � 1 � 1 � 1 �
  /Y7 �5   DS  16� /Y1       � 0 � 0 � 0 � 1 � OK � 1 � 0 � 1 � 1 � 1 �
  /Y6 �6  1211 15� /Y2       � 0 � . � . � . � OK � 1 � 1 � . � 1 � 1 �
   S2 �7       14� /Y3       � 0 � 1 � 1 � 1 � OK � 1 � 1 � 1 � 0 � 1 �
   S1 �8       13�           ������������������������������������������
   S0 �9       12� /Y4
  GND �10      11� /Y5
      ������������
#
DS1212
1-of-16 inverting decoder/nonvolatile SRAM controller chip.
TOL selects power-fail VCC level, based on 5% tolerance when 0 or
10% tolerance when 1.

      ��������������Ŀ        ���������������������������������������������Ŀ
VBAT1 �1    ����   28� VCC    �/EN� S3� S2� S1� S0�VCC �/Y0�/Y1�...�/Y15�/PF�
 VCCo �2           27� VBAT2  ���������������������������������������������͵
  TOL �3           26� /EN    � X � X � X � X � X � LO � 1 � 1 � 1 � 1  � 0 �
  /PF �4           25� /Y0    � 1 � 0 � 0 � 0 � 0 � OK � 0 � 1 � 1 � 1  � 1 �
 /Y15 �5           24� /Y1    � 0 � 0 � 0 � 0 � 1 � OK � 1 � 0 � 1 � 1  � 1 �
 /Y14 �6           23� /Y2    � 0 � . � . � . � . � OK � 1 � 1 � . � 1  � 1 �
 /Y13 �7     DS    22� /Y3    � 0 � 1 � 1 � 1 � 1 � OK � 1 � 1 � 1 � 0  � 1 �
 /Y12 �8    1212   21� /Y4    �����������������������������������������������
 /Y11 �9           20� /Y5
   S3 �10          19� /Y6
   S2 �11          18� /Y7
   S1 �12          17� /Y8
   S0 �13          16� /Y9
  GND �14          15� /Y10
      ����������������
#
DS1285, DS1287, DS1287A
Real-time clock with 50 bytes RAM.
DS1287(A) has built-in quartz crystal and lihium battery, and therefore
the X1, X2 and VBAT pins are no-connect.  On the (older) DS1287 the /RCLR
pin is no-connect as well.

    ��������������Ŀ
MOT �1    ����   24� VCC
 X1 �2           23� SQW
 X2 �3           22�
AD0 �4           21� /RCLR
AD1 �5           20� VBAT
AD2 �6   DS1285  19� /INT
AD3 �7           18� /RST
AD4 �8           17� DS
AD5 �9           16� GND
AD6 �10          15� R//W
AD7 �11          14� AS
GND �12          13� /CE
    ����������������
#
DS2009, DS2010, DS2011, DS2012, DS2013
512x9 (2009), 1024x9 (2010), 2048x9 (2011), 4096x9 (2012), 8192x9 (2013) FIFO.

      ��������������Ŀ
  /WR �1    ����   28� VCC
   D8 �2           27� D4
   D3 �3           26� D5
   D2 �4           25� D6
   D1 �5           24� D7
   D0 �6           23� /FL /RT
  /XI �7           22� /RST
/FULL �8   DS20xx  21� /EMPTY
   Q0 �9           20� /XO /HF
   Q1 �10          19� Q7
   Q2 �11          18� Q6
   Q3 �12          17� Q5
   Q8 �13          16� Q4
  GND �14          15� /RD
      ����������������
#
LF353
Dual JFET-input operational amplifiers.

     ����������Ŀ
1OUT �1  ����  8� VCC
-1In �2        7� 2OUT
+1In �3 LF353  6� -2In
 VEE �4        5� +2In
     ������������
#
LM317T
1.2 to 57V 1,5A positive power supply regulator.

TO 220
���Ŀ2
���͵
� ��
�����    1: Adj
 ���     2: Vout
 ���     3: Vin
1 2 3
#
LM334
Current mode temperature sensor.

TO 92
���ķ
� ��
���½    1: Iin
 ���     2: Rset
 ���     3: GND
1 2 3
#
LM337T
-1.2 to -57V 1,5A negative power supply regulator.

TO 220
���Ŀ2
���͵
� ��
�����    1: Adj
 ���     2: Vin
 ���     3: Vout
1 2 3
#
LM338
1.2 to 32V 5A positive power supply regulator.

TO 220
���Ŀ2
���͵
� ��
�����    1: Adj
 ���     2: Vout
 ���     3: Vin
1 2 3
#
LM34
Voltage mode temperature sensor.
Available in Fahrenheit or Celsius models and multiple temperature sense
ranges.  Output is 10mv/degree regardless of VCC (+5 to +30 V).

TO 92
���ķ
� ��
���½    1: VCC
 ���     2: Vout
 ���     3: GND
1 2 3
#
LM350
1.2 to 32V 3A positive power supply regulator.

TO 220
���Ŀ2
���͵
� ��
�����    1: Adj
 ���     2: Vout
 ���     3: Vin
1 2 3
#
LM837, LF347
Quad low-noise operational amplifiers.

     ����������Ŀ
1OUT �1  ���� 14� 4OUT
-1In �2       13� -4In
+1In �3       12� +4In
 VCC �4 LM837 11� VEE
+2In �5       10� +3In
-2In �6        9� -3In
2OUT �7        8� 3OUT
     ������������
#
MAX232
5V RS232 transceiver.
To operate, connect two 10� capacitors to the C1 and C2 pins, one between
the V- and GND, and one between V+ and GND.

      ����������Ŀ
  C1+ �1  ���� 16� VCC
   V+ �2       15� GND
  C1- �3       14� T1out
  C2+ �4  MAX  13� R1in
  C2- �5  232  12� R1out
   V- �6       11� T1in
T2out �7       10� T2in
 R2in �8        9� R2out
      ������������
#
MAX703
uP supervisor circuit with battery backup.
/RST remains low for 200ms after VCC exceeds 4.65V.  On power failure 
VCCo is connected to VBAT, PFI and /MR are disabled, /RST and /PFO are low.

     ����������Ŀ
VCCo �1  ����  8� VBAT
 VCC �2  MAX   7� /RST 
 GND �3  703   6� /MR
 PFI �4        5� /PFO 
     ������������
#
MC145436
DTMF decoder (Motorola)
DV goes high when a tone is detected on IN (-32..-2dB).
XEN is oscillator enable (pull high, and connect a Xtal // 1M resistor to
X1 and X2).  If XEN is low, ATB can be used to connect multiple chips
together.  GT determines the guard time, 0=short 1=long.

      ����������Ŀ
   D1 �1  ���� 14� D2
   D0 �2       13� D3
   OE �3       12� DV
  VCC �4  MC14 11� ATB
   GT �5  5436 10� X1
  XEN �6        9� X2
   IN �7        8� GND
      ������������
#
MCT9001
Dual optocouplers.

   ����������Ŀ
1A �1  ����  8� 1C
1K �2  MCT   7� 1E
2A �3  9001  6� 2C
2K �4        5� 2E
   ������������
#
MOC5010
Linear amplifier optocoupler.

  ����������Ŀ
A �1  ����  6� VCC
K �2  5010  5� GND
  �3        4� OUT
  ������������
#
PIC1654, PIC1656 (DIP)
MicroChip PIC microcontrollers.

     ����������Ŀ
 RA2 �1  ���� 18� RA1
 RA3 �2       17� RA0
RTCC �3       16� X1
/RST �4  PIC  15� X0
 GND �5 16C54 14� VCC
 RB0 �6 16C56 13� RB7
 RB1 �7       12� RB6
 RB2 �8       11� RB5
 RB3 �9       10� RB4
     ������������

#
PIC1654, PIC1656 (SO)
MicroChip PIC microcontrollers.

     ����������Ŀ
 RA2 �1  ���� 20� RA1
 RA3 �2       19� RA0
RTCC �3       18� X1
/RST �4  PIC  17� X0
 GND �5 16C54 16� VCC
 GND �6 16C55 15� VCC
 RB0 �7       14� RB7
 RB1 �8       13� RB6
 RB2 �9       12� RB5
 RB3 �10      11� RB4
     ������������
#
PIC1655, PIC1657 (DIP)
MicroChip PIC microcontrollers.

     ����������Ŀ
RTCC �1  ���� 28� /RST
 VCC �2       27� X1
     �3       26� X0
 GND �4       25� RC7
     �5       24� RC6
 RA0 �6  PIC  23� RC5
 RA1 �7 16C55 22� RC4
 RA2 �8 16C57 21� RC3
 RA3 �9       20� RC2
 RB0 �10      19� RC1
 RB1 �11      18� RC0
 RB2 �12      17� RB7
 RB3 �13      16� RB6
 RB4 �14      15� RB5
     ������������
#
PIC1655, PIC1657 (SO)
MicroChip PIC microcontrollers.

     ����������Ŀ
 GND �1  ���� 28� /RST
RTCC �2       27� X1
 VCC �3       26� X0
 VCC �4       25� RC7
 RA0 �5       24� RC6
 RA1 �6  PIC  23� RC5
 RA2 �7 16C55 22� RC4
 RA3 �8 16C57 21� RC3
 RB0 �9       20� RC2
 RB1 �10      19� RC1
 RB2 �11      18� RC0
 RB3 �12      17� RB7
 RB4 �13      16� RB6
 GND �14      15� RB5
     ������������
#
PIC1671, PIC1684
MicroChip PIC microcontrollers.

     ����������Ŀ
 RA2 �1  ���� 18� RA1
 RA3 �2       17� RA0
RTCC �3       16� X1
/RST �4  PIC  15� X0
 GND �5 16C71 14� VCC
 RB0 �6 16C84 13� RB7
 RB1 �7       12� RB6
 RB2 �8       11� RB5
 RB3 �9       10� RB4
     ������������
#
SIMM30
8/9-bit 30-pin Single Inline Memory Module.
If present, the ninth (parity) bit has separate data I/O and /CAS signals.
At one time, SIMMs with soldered-on pins (called SIPs) were also available.
Note: A11 is used as a battery connection in the DS2219 nonvolatile DRAM.

         �������Ŀ
      1  �   O   �
      ����       �
  VCC �� ������Ŀ�
 /CAS �� �      ��
   D0 �� �������ٳ
   A0 �� ������Ŀ�
   A1 �� �      ��
   D1 �� �������ٳ
   A2 �� ������Ŀ�
   A3 �� �      ��
  GND �� �������ٳ
   D2 �� ������Ŀ�
   A4 �� �      ��
   A5 �� �������ٳ
   D3 �� ������Ŀ�
   A6 �� �      ��
   A7 �� �������ٳ
   D4 �� ������Ŀ�
   A8 �� �      ��
   A9 �� �������ٳ
  A10 �� ������Ŀ�
   D5 �� �      ��
  /WR �� �������ٳ
  GND �� ������Ŀ�
   D6 �� �      ��
  A11 �� �������ٳ
   D7 ��         �
   Q8 �� ������Ŀ�
 /RAS �� �Parity��
/CAS8 �� �������ٳ
   D8 ��         �
  VCC ��         �
      ��Ŀ       �
      30 �   O   �
         ���������
#
TIL111, TIL112, TIL116, TIL117, TIL118, TIL124, TIL125, TIL126, CNY17, 4N25
Optocoupler.

  ����������Ŀ
A �1  ����  6� B
K �2        5� C
  �3        4� E
  ������������
#
TIL113, TIL119
Optocoupler with darlington transistor output configuration.

  ����������Ŀ
A �1  ����  6� B
K �2        5� C
  �3        4� E
  ������������
#
TL074
Quad low-noise JFET-input operational amplifiers.

     ����������Ŀ
1OUT �1  ���� 14� 4OUT
-1In �2       13� -4In
+1In �3       12� +4In
 VCC �4 TL074 11� VEE
+2In �5       10� +3In
-2In �6        9� -3In
2OUT �7        8� 3OUT
     ������������
#
TL084
Quad JFET-input operational amplifiers.

     ����������Ŀ
1OUT �1  ���� 14� 4OUT
-1In �2       13� -4In
+1In �3       12� +4In
 VCC �4 TL084 11� VEE
+2In �5       10� +3In
-2In �6        9� -3In
2OUT �7        8� 3OUT
     ������������
#
TL507, TL507C
7-bit PWM output analog-to-digital converter.
Only one of the two power supply pins should be used, 3.5V < VCC < 6V;
8V < VDD < 18V.  At VCC=5V the analog input range is 1.3V < AIN < 3.9V,
or about 25%...75%.  The RST pin can be used to synchronize the output
signal to an external counter; otherwise leave RST tied to VCC.

     ����������Ŀ
  EN �1  ����  8� RST
 CLK �2  TL    7� VDD
 GND �3  507   6� VCC
/OUT �4        5� AIN
     ������������
#
TL783C
1.3 to 125V 700mA high voltage positive power supply regulator.

TO 220
���Ŀ2
���͵
� ��
�����    1: Adj
 ���     2: Vout
 ���     3: Vin
1 2 3
#
TP5088
DTMF encoder (NatSemi).
When /SNGL is low, only the upper or lower tone (selected by GRP) is given.
OUT is open emitter, connect load to GND.

      ����������Ŀ
  VCC �1  ���� 14� OUT
   LE �2       13�
/SNGL �3       12� D3
  GRP �4  5088 11� D2
  GND �5       10� D1
   X1 �6        9� D0
   X0 �7        8� MUTE
      ������������
#
UDN2585
7-bit 50V 500mA TTL-input PNP (high-side) darlington driver.
The drivers need no power supply; the GND pin is the common anode of the
seven integrated protection diodes.

    ����������Ŀ             �������Ŀ
 A0 �1  ���� 16� /Y0         � A �/Y �
 A1 �2       15� /Y1         �������͵
 A2 �3       14� /Y2         � 0 � Z �
 A3 �4  UDN  13� /Y3         � 1 � 0 �
 A4 �5  2585 12� /Y4         ���������
 A5 �6       11� /Y5
 A6 �7       10� /Y6
VCC �8        9� GND
    ������������
#
ULN2003, MC1413
7-bit 50V 500mA TTL-input NPN darlington driver.
The drivers need no power supply; the VDD pin is the common cathode of the
seven integrated protection diodes.

    ����������Ŀ             �������Ŀ
 A0 �1  ���� 16� /Y0         � A �/Y �
 A1 �2       15� /Y1         �������͵
 A2 �3       14� /Y2         � 0 � Z �
 A3 �4  ULN  13� /Y3         � 1 � 0 �
 A4 �5  2003 12� /Y4         ���������
 A5 �6       11� /Y5
 A6 �7       10� /Y6
GND �8        9� VDD
    ������������
#
ULN2803
8-bit 50V 500mA TTL-input NPN darlington driver.
The drivers need no power supply; the VDD pin is the common cathode of the
eight integrated protection diodes.

    ����������Ŀ             �������Ŀ
 A0 �1  ���� 18� /Y0         � A �/Y �
 A1 �2       17� /Y1         �������͵
 A2 �3       16� /Y2         � 0 � Z �
 A3 �4  ULN  15� /Y3         � 1 � 0 �
 A4 �5  2803 14� /Y4         ���������
 A5 �6       13� /Y5
 A6 �7       12� /Y6
 A7 �8       11� /Y7
GND �9       10� VDD
    ������������