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Document Title: [6502ref.html (html file)]

65C02 Reference Manual

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Table of Contents:

1. General Overview
2. Instruction Set
3. Addressing Modes
4. Instruction Encodings
5. Examples

General Overview

The Western Design Center, Inc. (WDC) of Mesa, AZ, is the original designer and intellectual property owner of the 65C02. You can get official information about WDC and their products by visiting their web page.

The 65C02 has a 16 bit address space (64K) arranged in 256 pages each of which is 256 bytes long.

Page 0 ($0000-$00FF) has some special properties involving addressing modes and is very valuable memory.

Page 1 ($0100-$01FF) is the stack.

Bytes $FFFA-$FFFB are the NMIB interrupt vector.
Bytes $FFFC-$FFFD are the reset vector.
Bytes $FFFE-$FFFF are the IRQ/BRK vector.

The 65C02 has 3 registers, stack pointer, processor flags (P), and program counter. The registers are the Accumulator (A), X index, and Y index. Each is 8 bits wide. Most instructions leave results in the accumulator. The stack pointer is an 8 bit register that is used as an offset into the stack (page 1). It is auto incrementing and decrementing when used with the push and pull (pop) instructions. You can also directly access and modify it's value via the TSX and TXS instructions.

The P register contains the following one bit flags:

Negative (N)

Set when the result of an operation leaves the high bit set. Cleared otherwise.

Overflow (V)

Set when there is a borrow or carry out of an operation.

Break (B)

Set when a 'BRK' instruction is encountered.

Decimal (D)

When set all arithmatic is BCD (ie. 09+01=10). When clear all arithmatic is binary 2s complement (ie. 09+01=0A).

Interrupt Disable (I)

When set no interrupts can occur.

Zero (Z)

Set when the result of an operation is zero. Cleared otherwise.

Carry (C)

Set when there is a carry. (more here)

The bit's are arranged as follows (from 7 [highest] to 0 [lowest]): NV-BDIZC

Instruction Set

Mnemonic	Description	Flags
Load & Store Instructions
LDA	load accumulator	NZ
LDX	load X index	NZ
LDY	load Y index	NZ
STA	store accumulator	-
STX	store X index	-
STY	store Y index	-
STZ	store zero	-
Stack Operations
PHA	push accumulator	-
PHX	push X index	-
PHY	push Y index	-
PHP	push processor flags	-
PLA	pull (pop) accumulator	NZ
PLX	pull (pop) X index	NZ
PLY	pull (pop) Y index	NZ
PLP	pull (pop) processor flags	All
TSX	transfer stack pointer to X	NZ
TXS	transfer stack pointer to X	-
Increment & Decrement Operations
INA	increment accumulator	NZ
INX	increment X index	NZ
INY	increment Y index	NZ
DEA	decrement accumulator	NZ
DEX	decrement X index	NZ
DEY	decrement Y index	NZ
INC	increment memory location	NZ
DEC	decrement memory location	NZ
Shift Operations
ASL	arithmetic shift left, high bit into carry	NZC
LSR	logical shift right, low bit into carry	N=0 ZC
ROL	rotate left through carry	NZC
ROR	rotate right through carry	NZC
Logical Operations
AND	and accumulator	NZ
ORA	or accumulator	NZ
EOR	exclusive-or accumulator	NZ
BIT	test bits against accumulator (1)	N=M7 V=M6 Z
CMP	compare with accumulator	NZC
CPX	compare with X index	NZC
CPY	compare with Y index	NZC
TRB	test and reset bits	x
TSB	test and set bits	x
RMB	reset memory bit	x
SMB	reset memory bit	x
Math Operations
ADC	add accumulator, with carry	NZCV
SBC	subtract accumulator, with borrow	NZCV
Flow Control Instructions
JMP	unconditional jump	-
JSR	jump Subroutine	-
RTS	return from Subroutine	-
RTI	return from Interrupt	From Stack
BRA	branch Always	-
BEQ	branch on equal (zero set)	-
BNE	branch on not equal (zero clear)	-
BCC	branch on carry clear (2)	-
BCS	branch on carry set (2)	-
BVC	branch on overflow clear	-
BVS	branch on overflow set	-
BMI	branch on minus	-
BPL	branch on plus	-
BBR	branch on bit reset (zero)	-
BBS	branch on bit set (one)	-
Processor Status Instructions
CLC	clear carry flag	C=0
CLD	clear decimal mode	D=0
CLI	clear interrupt disable bit	I=0
CLV	clear overflow flag	V=0
SEC	set carry flag	C=1
SED	set decimal mode	D=1
SEI	set interrupt disable bit	I=1
Transfer Instructions
TAX	transfer accumulator to X index	NZ
TAY	transfer accumulator to Y index	NZ
TXA	transfer X index to accumulator	NZ
TYA	transfer Y index to accumulator	NZ
Misc Instructions
NOP	no operation	-
BRK	force break	B=1

Notes:

1. The BIT instruction copies bit 6 to the V flag, and bit 7 to the N flag (except in immediate addressing mode where V & N are untouched.) The accumulator and the operand are ANDed and the Z flag is set appropriately.
2. The BCC & BCS instructions instructions are sometimes known as BLT (branch less than) and BGE (branch greater or equal), respectively.

Addressing Modes

There are fifteen addressing modes available. They are:

Implied Addressing [Implied]

In the implied addressing mode, the address containing the operand is implicitly stated in the operation code of the intruction.

Accumulator Addressing [Accumulator]

This form of addressing is represented with a one byte instruction and implies an operation on the accumulator.

Immediate Addressing [Immediate]

With immediate addressing, the operand is contained in the second byte of the instruction; no further memory addressing is required.

Absolute Addressing [Absolute]

For absolute addressing, the second byte of the instruction specifies the eight low-order bits of the effective address, while the third byte specifies the eight high-order bits. Therefore, this addressing mode allows access to the total 64K bytes of addressable memory.

Zero Page Addressing [Zero Page]

Zero page addressing allows shorter code and execution times by only fetching the second byte of the instruction and assuming a zero high address byte. The careful use of zero page addressing can result in significant increase in code efficiency.

Absolute Indexed Addressing [Absolute,X or Absolute,Y]

Absolute indexed addressing is used in conjunction with X or Y index register and is referred to as "Absolute, X," and "Absolute, Y." The effective address is formed by adding the contents of X or Y to the address contained in the second and third bytes of the instruction. This mode allows the index register to contain the index or count value and the instruction to contain the base address. This type of indexing allows any location referencing and the index to modify multiple fields, resulting in reduced coding and instruction time.

Zero Page Indexed Addressing [Zero Page,X or Zero Page,Y]

Zero page indexed addressing is used in conjunction with the index register and is referred to as "Zero Page, X" or "Zero Page, Y." The effective address is calculated by adding the second byte to the contents of the indexed register. Since this is a form of "Zero Page" addressing, the content of the second byte references a location in page zero. Additionally, due to the "Zero Page" addressing nature of this mode, no carry is added to the high-order eight bits of memory, and crossing of page boundaries does not occur.

Relative Addressing [Relative]

Relative addressing is used only with branch instructions; it establishes a destination for the conditional branch. The second byte of the instruction becomes the operand which is an "Offset" added to the contents of the program counter when the program counter is set at the next instruction. The range of the offset is -128 to 127 bytes from the next instruction.

Zero Page Indexed Indirect Addressing [(Zero Page,X)]

With zero page indexed indirect addressing (usually referred to as indirect X) the second byte of the instruction is added to the contents of the X index register; the carry is discarded. The result of this addition points to a memory location on page zero whose contents is the low-order eight bits of the effective address. The next memory location in page zero contains the high-order eight bits of the effective address. Both memory locations specifying the high- and low-order bytes of the effective address must be in page zero.

Absolute Indexed Indirect Addressing [(Absolute,X)]

(Jump Instruction Only) With absolute indexed indirect addressing the contents of the second and third instruction bytes are added to the X register. The result of this addition, points to a memory location containing the low-order eight bits of the effective address. The next memory location contains the higher-order eight bits of the effective address.

Indexed Indirect Addressing [(Zero Page),Y]

This form of addressing is usually referred to as Indirect, Y. The second byte of the instruction points to a memory location in page zero. The contents of this memory location are added to the Y index register, the result being the low-order eight bits of the effective address. The carry from this addition is added to the contents of the next page zero memory location, the result being the high-order eight bits of the effective address.

Zero Page Indirect Addressing [(Zero Page)]

In the zero page indirect addressing mode, the second byte of the instruction points to a memory location on page zero containing the low-order byte of the effective address. The next location on page zero contains the high-order byte of the effective address.

Absolute Indirect Addressing [(Absolute)]

(Jump Instruction Only) The second byte of the instruction contains the low-order eight bits of a memory location. The high-order eight bits of that memory location is contained in the third byte of the instruction. The contents of the fully specified memory location is the low-order byte of the effective address. The next memory location contains the high-order byte of the effective address which is loaded into the 16 bit program counter.

Instruction Encodings

Mnemonic	Addressing mode	Form	Opcode	Size	Timing
ADC	Immediate	ADC #Oper	69	2	2
	Zero Page	ADC Zpg	65	2	3
	Zero Page,X	ADC Zpg,X	75	2	4
	Absolute	ADC Abs	6D	3	4
	Absolute,X	ADC Abs,X	7D	3	4
	Absolute,Y	ADC Abs,Y	79	3	4
	(Zero Page,X)	ADC (Zpg,X)	61	2	6
	(Zero Page),Y	ADC (Zpg),Y	71	2	5
	(Zero Page)	ADC (Zpg)	72	2	5
AND	Immediate	AND #Oper	29	2	2
	Zero Page	AND Zpg	25	2	3
	Zero Page,X	AND Zpg,X	35	2	4
	Absolute	AND Abs	2D	3	4
	Absolute,X	AND Abs,X	3D	3	4
	Absolute,Y	AND Abs,Y	39	3	4
	(Zero Page,X)	AND (Zpg,X)	21	2	6
	(Zero Page),Y	AND (Zpg),Y	31	2	5
	(Zero Page)	AND (Zpg)	32	2	5
ASL	Accumulator	ASL A	0A	1	2
	Zero Page	ASL Zpg	06	2	5
	Zero Page,X	ASL Zpg,X	16	2	6
	Absolute	ASL Abs	0E	3	6
	Absolute,X	ASL Abs,X	1E	3	7
BBR0	Relative	BBR0 Oper	0F	2	2
BBR1	Relative	BBR1 Oper	1F	2	2
BBR2	Relative	BBR2 Oper	2F	2	2
BBR3	Relative	BBR3 Oper	3F	2	2
BBR4	Relative	BBR4 Oper	4F	2	2
BBR5	Relative	BBR5 Oper	5F	2	2
BBR6	Relative	BBR6 Oper	6F	2	2
BBR7	Relative	BBR7 Oper	7F	2	2
BBS0	Relative	BBS0 Oper	8F	2	2
BBS1	Relative	BBS1 Oper	9F	2	2
BBS2	Relative	BBS2 Oper	AF	2	2
BBS3	Relative	BBS3 Oper	BF	2	2
BBS4	Relative	BBS4 Oper	CF	2	2
BBS5	Relative	BBS5 Oper	DF	2	2
BBS6	Relative	BBS6 Oper	EF	2	2
BBS7	Relative	BBS7 Oper	FF	2	2
BCC	Relative	BCC Oper	90	2	2
BCS	Relative	BCS Oper	B0	2	2
BEQ	Relative	BEQ Oper	F0	2	2
BIT	Immediate	BIT #Oper	89	2	2
	Zero Page	BIT Zpg	24	2	3
	Zero Page,X	BIT Zpg,X	34	2	4
	Absolute	BIT Abs	2C	3	4
	Absolute,X	BIT Abs,X	3C	3	4
BMI	Relative	BMI Oper	30	2	2
BNE	Relative	BNE Oper	D0	2	2
BPL	Relative	BPL Oper	10	2	2
BRA	Relative	BRA Oper	80	2	3
BRK	Implied	BRK	00	1	7
BVC	Relative	BVC Oper	50	2	2
BVS	Relative	BVS Oper	70	2	2
CLC	Implied	CLC	18	1	2
CLD	Implied	CLD	D8	1	2
CLI	Implied	CLI	58	1	2
CLV	Implied	CLV	B8	1	2
CMP	Immediate	CMP #Oper	C9	2	2
	Zero Page	CMP Zpg	C5	2	3
	Zero Page,X	CMP Zpg	D5	2	4
	Absolute	CMP Abs	CD	3	4
	Absolute,X	CMP Abs,X	DD	3	4
	Absolute,Y	CMP Abs,Y	D9	3	4
	(Zero Page,X)	CMP (Zpg,X)	C1	2	6
	(Zero Page),Y	CMP (Zpg),Y	D1	2	5
	(Zero Page)	CMP (Zpg)	D2	2	5
CPX	Immediate	CPX #Oper	E0	2	2
	Zero Page	CPX Zpg	E4	2	3
	Absolute	CPX Abs	EC	3	4
CPY	Immediate	CPY #Oper	C0	2	2
	Zero Page	CPY Zpg	C4	2	3
	Absolute	CPY Abs	CC	3	4
DEA	Accumulator	DEA	3A	1	2
DEC	Zero Page	DEC Zpg	C6	2	5
	Zero Page,X	DEC Zpg,X	D6	2	6
	Absolute	DEC Abs	CE	3	6
	Absolute,X	DEC Abs,X	DE	3	7
DEX	Implied	DEX	CA	1	2
DEY	Implied	DEY	88	1	2
EOR	Immediate	EOR #Oper	49	2	2
	Zero Page	EOR Zpg	45	2	3
	Zero Page,X	EOR Zpg,X	55	2	4
	Absolute	EOR Abs	4D	3	4
	Absolute,X	EOR Abs,X	5D	3	4
	Absolute,Y	EOR Abs,Y	59	3	4
	(Zero Page,X)	EOR (Zpg,X)	41	2	6
	(Zero Page),Y	EOR (Zpg),Y	51	2	5
	(Zero Page)	EOR (Zpg)	52	2	5
INA	Accumulator	INA	1A	1	2
INC	Zero Page	INC Zpg	E6	2	5
	Zero Page,X	INC Zpg,X	F6	2	6
	Absolute	INC Abs	EE	3	6
	Absolute,X	INC Abs,X	FE	3	7
INX	Implied	INX	E8	1	2
INY	Implied	INY	C8	1	2
JMP	Absolute	JMP Abs	4C	3	3
	(Absolute)	JMP (Abs)	6C	3	5
	(Absolute,X)	JMP (Abs,X)	7C	3	6
JSR	Absolute	JSR Abs	20	3	6
LDA	Immediate	LDA #Oper	A9	2	2
	Zero Page	LDA Zpg	A5	2	3
	Zero Page,X	LDA Zpg,X	B5	2	4
	Absolute	LDA Abs	AD	3	4
	Absolute,X	LDA Abs,X	BD	3	4
	Absolute,Y	LDA Abs,Y	B9	3	4
	(Zero Page,X)	LDA (Zpg,X)	A1	2	6
	(Zero Page),Y	LDA (Zpg),Y	B1	2	5
	(Zero Page)	LDA (Zpg)	B2	2	5
LDX	Immediate	LDX #Oper	A2	2	2
	Zero Page	LDX Zpg	A6	2	3
	Zero Page,Y	LDX Zpg,Y	B6	2	4
	Absolute	LDX Abs	AE	3	4
	Absolute,Y	LDX Abs,Y	BE	3	4
LDY	Immediate	LDY #Oper	A0	2	2
	Zero Page	LDY Zpg	A4	2	3
	Zero Page,Y	LDY Zpg,X	B4	2	4
	Absolute	LDY Abs	AC	3	4
	Absolute,Y	LDY Abs,X	BC	3	4
LSR	Accumulator	LSR A	4A	1	2
	Zero Page	LSR Zpg	46	2	5
	Zero Page,X	LSR Zpg,X	56	2	6
	Absolute	LSR Abs	4E	3	6
	Absolute,X	LSR Abs,X	5E	3	7
NOP	Implied	NOP	EA	1	2
ORA	Immediate	ORA #Oper	09	2	2
	Zero Page	ORA Zpg	05	2	3
	Zero Page,X	ORA Zpg,X	15	2	4
	Absolute	ORA Abs	0D	3	4
	Absolute,X	ORA Abs,X	1D	3	4
	Absolute,Y	ORA Abs,Y	19	3	4
	(Zero Page,X)	ORA (Zpg,X)	01	2	6
	(Zero Page),Y	ORA (Zpg),Y	11	2	5
	(Zero Page)	ORA (Zpg)	12	2	5
PHA	Implied	PHA	48	1	3
PHX	Implied	PHX	DA	1	3
PHY	Implied	PHY	5A	1	3
PLA	Implied	PLA	68	1	4
PLX	Implied	PLX	FA	1	4
PLY	Implied	PLY	7A	1	4
ROL	Accumulator	ROL A	2A	1	2
	Zero Page	ROL Zpg	26	2	5
	Zero Page,X	ROL Zpg,X	36	2	6
	Absolute	ROL Abs	2E	3	6
	Absolute,X	ROL Abs,X	3E	3	7
ROR	Accumulator	ROR A	6A	1	2
	Zero Page	ROR Zpg	66	2	5
	Zero Page,X	ROR Zpg,X	76	2	6
	Absolute	ROR Abs	6E	3	6
	Absolute,X	ROR Abs,X	7E	3	7
RTI	Implied	RTI	40	1	6
RTS	Implied	RTS	60	1	6
SBC	Immediate	SBC #Oper	E9	2	2
	Zero Page	SBC Zpg	E5	2	3
	Zero Page,X	SBC Zpg,X	F5	2	4
	Absolute	SBC Abs	ED	3	4
	Absolute,X	SBC Abs,X	FD	3	4
	Absolute,Y	SBC Abs,Y	F9	3	4
	(Zero Page,X)	SBC (Zpg,X)	E1	2	6
	(Zero Page),Y	SBC (Zpg),Y	F1	2	5
	(Zero Page)	SBC (Zpg)	F2	2	5
SEC	Implied	SEC	38	1	2
SED	Implied	SED	F8	1	2
SEI	Implied	SEI	78	1	2
STA	Zero Page	STA Zpg	85	2	3
	Zero Page,X	STA Zpg,X	95	2	4
	Absolute	STA Abs	8D	3	4
	Absolute,X	STA Abs,X	9D	3	5
	Absolute,Y	STA Abs,Y	99	3	5
	(Zero Page,X)	STA (Zpg,X)	81	2	6
	(Zero Page),Y	STA (Zpg),Y	91	2	6
	(Zero Page)	STA (Zpg)	92	2	5
STX	Zero Page	STX Zpg	86	2	3
	Zero Page,Y	STX Zpg,Y	96	2	4
	Absolute	STX Abs	8E	3	4
STY	Zero Page	STY Zpg	84	2	3
	Zero Page,X	STY Zpg,X	94	2	4
	Absolute	STY Abs	8C	3	4
STZ	Zero Page	STZ Zpg	64	2	3
	Zero Page,X	STZ Zpg,X	74	2	4
	Absolute	STZ Abs	9C	3	4
	Absolute,X	STZ Abs,X	9E	3	5
TAX	Implied	TAX	AA	1	2
TAY	Implied	TAY	A8	1	2
TRB	Zero Page	TRB Zpg	14	2	5
	Absolute	TRB Abs	1C	3	6
TSB	Zero Page	TSB Zpg	04	2	5
	Absolute	TSB Abs	0C	3	6
TSX	Implied	TSX	BA	1	2
TXA	Implied	TXA	8A	1	2
TXS	Implied	TXS	9A	1	2
TYA	Implied	TYA	98	1	2